Abstract: An information handling system executing a reinforcement learning (RL) based data center power consumption minimizing system may comprise a network interface device to receive operational telemetry measurements for a plurality of data center processors forming a processing node, including performance and utilization analytics, and a user-specified low-utility threshold value, a hardware processor to predict a future time window in which a utilization rate for the processing node executing a future workload falls below the user-specified low-utility threshold value, the hardware processor to identify an optimal load-balancing instruction for redistributing the future workload across a sub-portion of the processing system associated with a highest reward value for satisfying quality of service (QoS) requirements, and the network interface device to transmit the optimal load-balancing instruction and an instruction to throttle power supplied to a remainder of the processing system.

Abstract: A system is described. The system includes at least one power supply, a control system communicatively coupled to the at least one power supply, a communication module, and at least one channel connecting the at least one power supply to the communication module. The at least one channel is also configured to support communication according to a particular communication protocol. The communication module is configured to interface with two or more power supplies of the at least one power supply via the at least one channel, and each power supply of the at least one power supply is configured to transmit diagnostic data associated with the power supply to the communication module via the at least one channel.

Abstract: An image processing method and apparatus for a mobile platform, a mobile platform, and a medium. The image processing method may include acquiring a current image to be encoded; acquiring an encoding quality evaluation parameter of an encoded historical image and a network state evaluation parameter of a wireless communication link, wherein the encoded historical image may be sent to a receiving end through the wireless communication link; and based on the encoding quality evaluation parameter and the network state evaluation parameter, determining whether to execute a target area image processing algorithm on the current image.

Abstract: Techniques for analyzing cache efficiencies in storage systems based on in-depth metrics instrumentation. The techniques include collecting metrics instrumentation data for each page of a specific type stored in a cache memory component of a storage system. The metrics instrumentation data for each page of a specific type includes a timestamp indicating when the page was stored in the cache, a timestamp indicating when the last cache hit occurred for the page, a current number of cache hits for the page, and an indication of the specific type of page. The techniques further include, based on the metrics instrumentation data, obtaining a plurality of metrics for each specific type of page stored in the cache. The techniques further include, based on the plurality of metrics and/or the metrics instrumentation data, performing a remedial action to improve performance of the cache memory component or provide more optimal use of memory resources.

Abstract: Systems and methods are disclosed for monitoring power usage and temperature within a data storage device, and adjusting performance based on the power usage and temperature. In certain embodiments, an apparatus may comprise a data storage device (DSD) having an interface to communicate with a host device, and a circuit. The circuit may be configured to receive a first limit designation for a first operating parameter of the DSD via the interface, monitor a value of the first operating parameter of the DSD, evaluate a pending workload of operations to be performed by the DSD, estimate a future value of the first operating parameter based on the pending workload, and adjust performance of the DSD based on the future value and the first limit designation.

Abstract: There is described a color-changing LED bulb in the LED bulb technical field. The bulb has light-emitting components, under which electrified components are mounted. The outer surface of the light-emitting component is covered by a lampshade. The light-emitting component includes a component loading board with a protective cover on the outer side. The power cord stretches out of the bottom of the loading board and is connected to electrified components. Capacitors are also mounted at the bottom of the loading board. This color changing LED bulb controls the power supply to the beads via a chip bridge rectifier, chip resistor, and IC chip. If the switch is flipped, the chip bridge rectifier detects if power is supplied. By connecting the 3 different IC chips—U1, U2 & U3, U1 chip controls the U2 & U3 IC chip to electrify the beads of different colors. Each time that the switch is operated (flipped), a different color is displayed.

Abstract: A dongle coupled between a power supplying device for supplying power and a power receiving device for receiving power includes a downstream facing port (DFP), an upstream facing port (UFP) and a controller. The controller is arranged to control deliveries of the power and messages between the power supplying device and the power receiving device. In response to a first power request message received from the power receiving device, the controller is arranged to determine whether a power type request by the power receiving device is Programmable Power Supply (PPS) according to the first power request message. When determining that the power type request by the power receiving device is PPS, the controller is arranged to start first waiting timer, and when the first waiting timer expires, the controller is arranged to send a request accept message to the power receiving device through the UFP.

Abstract: Described aspects include a system for optimizing performance of a functional circuit unit, a method of optimizing performance of a functional circuit unit, and a computer program product. In one embodiment, the system may include a functional circuit unit having an associated cooling device and power converter, one or more sensors for the functional circuit unit, the one or more sensors including a power sensor and a temperature sensor, and a first machine learning model. The first machine learning model may be adapted to receive temperature data and power data from the one or more sensors, and to generate control signals for the cooling device and the power converter to optimize performance of the functional circuit unit.

Abstract: In one embodiment, a method includes receiving low voltage pulse power from power sourcing equipment at a powered device, synchronizing the powered device with a waveform of the low voltage pulse power received from the power sourcing equipment, and operating the powered device with high voltage pulse power received from the power sourcing equipment.

Abstract: Managing power consumption for computing cluster, including for each IHS of the computing cluster: executing I/O computing workloads at the IHS associated with movement of block storage data, stored at a disk array in communication with the IHS, between the disk array and the IHS; during execution of the I/O computing workloads, determining an I/O power usage of the IHS; calculating an accumulated I/O power consumption of the plurality of IHS based on a summation of the I/O power usage of each of the IHS; during movement of the block storage data, calculating a power consumption of the disk array; calculating, for each IHS, a power storage consumption of the IHS based on the I/O power usage of the IHS, the accumulated I/O power consumption, and the power consumption of the disk array; allocating additional workloads among the plurality of IHS based on the power storage consumption of each IHS.

Abstract: The power supply system comprises an inter-system bus, one or more renewable energy systems and one or more second switches, where each second switch is coupled to one renewable energy system and to connect to the corresponding renewable energy system to the inter-system bus. The power supply system further comprises one or more current detection circuits, where each current detection circuit is coupled to one renewable energy system to detect an output current of the corresponding renewable energy system. The power supply system further comprises a central controller coupled to the inter-system bus and configured to, in response to the output current of the corresponding renewable energy system is higher than a predetermined threshold current, activate a corresponding second switch to connect the corresponding renewable energy system to the inter-system bus to provide a renewable power to at least one of the one or more server clusters, or storage systems.

Abstract: A system including a lighting controller and a radio adapter. The lighting controller includes a smart port and is configured to control at least one lighting fixture. The radio adapter is communicatively coupled to the lighting controller via the smart port. The radio adapter is configured to establish a wireless communication link between the lighting controller and an external device, communicatively couple the external device to the lighting controller via the smart port, and provide a master clock timing signal to the lighting controller via the smart port.

Abstract: A system performs adaptive thermal ceiling control at runtime. The system includes computing circuits and a thermal management module. When detecting a runtime condition change that affects power consumption in the system, the thermal management module determines an adjustment to the thermal ceiling of a computing circuit, and increases the thermal ceiling of the computing circuit according to the adjustment.

Abstract: Systems, methods, and computer-readable media are disclosed for modeled advertisement conversion attributions. An example method may include receiving first input data comprising first advertisement impression data and first advertisement conversion data, wherein the first input data includes one or more user identifiers associated with both the advertisement impression data and advertisement conversion data. The example method may also include training one or more machine learning models using the first input data. The example method may also include receiving second input data comprising second advertisement impression data, wherein user identifiers are unavailable for the second input data. The example method may also include determining, using the one or more machine learning models, second predicted conversion data associated with the second input data.

Abstract: The present disclosure relates to a polarity correction circuit. The polarity correction circuit may include a detection module and a switching module. The detection module may be configured to detect a polarity of a DC voltage transmitted to a powered device and generate one or more control signals based on the polarity of the DC voltage. The switching module may be configured to receive the one or more control signals and a data signal transmitted from the powered device. The switching module may be further configured to adapt a polarity of the data signal based on the one or more control signals such that the polarity of the data signal is accordant with the polarity of the DC voltage.

Abstract: A memory device includes memory dice, each memory die including: a memory array; a memory to store a data structure; and control logic that includes: multiple processing threads to execute memory access operations on the memory array concurrently; a priority ring counter, the data structure to store an association between a value of the priority ring counter and a subset of the multiple processing threads; a threads manager to increment the value of the priority ring counter before a power management cycle and to identify one or more prioritized processing threads corresponding to the subset of the multiple processing threads; and a peak power manager coupled with the threads manager and to prioritize allocation of power to the one or more prioritized processing threads during the power management cycle.

Abstract: A system for controlling power settings is provided that includes a plurality of components, each component configured to implement a power control algorithm. A controller is coupled to each component and configured to control a power state of each component as a function of the power control algorithm for each component. The controller comprises a state machine having a plurality of states, wherein the power control algorithm of each component is controlled by the controller as a function of a state of the state machine.

Abstract: According to an embodiment, an electronic device may include: a power management module; a USB connection terminal; a processor operably connected to the power management module and the USB connection terminal; and a memory operably connected to the processor. The memory may store instructions that, when executed, cause the processor to: provide, in response to connection with an external electronic device through the USB connection terminal, fast charging related information to the external electronic device; obtain power based on the fast charging related information from the external electronic device; perform a fast charging operation through the power management module based on the obtained power; determine to enter a first mode for data communication with the external electronic device; and determine whether fast charging is possible in the external electronic device based on the obtained power and an entry into the first mode by the electronic device and the external electronic device.

Abstract: The present invention disclosures a current calibration device for power supply channels in a test system, comprising n power supply channels, n connection switches corresponding to the n power supply channels, m resistors, m selection switches corresponding to the m resistors, a VBIAS power supply, a SPI bus, a host computer and an ammeter, wherein, both n and m are integers greater than 0; one end of each of the n power supply channels is connected to the SPI bus, and another end of each of the n power supply channels is connected to a node Q through a connection switch correspondingly, both ends of the selection switch are connected respectively to the node Q and one end of the resistor, and another end of the resistor is connected to the positive terminal of the ammeter, and the negative terminal of the ammeter is connected to the VBIAS power supply, and the VBIAS power supply is connected to the SPI bus simultaneously.

Abstract: The disclosed Security Hardware/Software simultaneously triggers a mild yet effective shock to the invader's fingers, while completely shutting down the device that is being targeted for hacking. A first system interrupt based on a first unsuccessful login into the computer system, and configured to display a warning message to a user on a screen in communication with a keyboard of the computer system. The deterrent shock is delivered to the user based on the first system interrupt. A second system interrupt based on a second unsuccessful login, and configured to trigger an alarm and lock down computer system devices and inform a law enforcement agency of the second system interrupt. A third system interrupt is based on a third unsuccessful login. The third system interrupt is configured to accept a secure pass code from a vendor of the system to restore the system to a preinterrupt condition.

Abstract: An information processing apparatus includes a processor configured to, when connected devices whose number is greater than a predetermined number are connected to the information processing apparatus, the predetermined number indicating the maximum number of devices simultaneously supplied with power, switch a power supply destination between the connected devices so as to obtain a state in which the number of connected devices simultaneously supplied with power is equal to or less than the predetermined number.

Abstract: A power supply apparatus, including: a first power supply component, a power over Ethernet (POE) component, a second power supply component, a first controller, and a power supply path management component. The first power supply component is respectively connected to the first controller and the power supply path management component, the POE component is connected to the first controller, and the first controller and the second power supply component are respectively connected to the power supply path management component. The first controller is configured to: detect whether the first power supply component supplies power; close a power supply path of the POE component when the first power supply component supplies power normally; and control the power supply path management component to open a power supply path of the second power supply component when the POE component supplies power abnormally and the first power supply component does not supply power.

Abstract: The technology described herein is directed towards optimizing power consumption of devices, e.g., in a datacenter. A modified (two-tier) genetic algorithm performs a carbon footprint-based optimization in a first tier to determine a candidate range of coefficients for each device type, e.g., servers, switches and storage devices/systems that likely reduce carbon footprint of each device type. In a second tier of the genetic algorithm, those ranges of coefficients are used in conjunction with actual power usage-based carbon footprint scores of individual devices to find respective sets of coefficients that minimize respective objective functions for the servers, the switches and the storage devices. The sets of coefficients can be used for power capping the devices. Device performance constraint-based intelligent selection can be used in one or both tiers to speed up convergence.

Abstract: Techniques for predictive autoscaling and resource optimization of software deployments. In an implementation, users declare performance objectives, and machine learning of application behavior and load profile is to used to determine minimum cost resourcing to meet the declared performance objectives. In an embodiment, convergent deployments are monitored and related feedback is provided to improve forecasting, behavior modeling, and resource estimation over time.

Abstract: A fan control system for use in a server system is disclosed. The fan control system includes a first monitoring and protection chip, a second monitoring and protection chip, a switch, a plurality of fans and a complex programmable logic device (CPLD). In a shutdown state of the server system, the switch is switched under control of the CPLD so that the fans are connected to the second monitoring and protection chip, receive standby power therefrom and run at a standby power level. When the server system is switched to a working state, the switch is switched under control of the CPLD so that the fans are connected to the first monitoring and protection chip, receive operating power therefrom and run at a higher working power level. This design can address different heat dissipation needs of various applications.

Abstract: A memory controller component of a memory system stores memory access requests within a transaction queue until serviced so that, over time, the transaction queue alternates between occupied and empty states. The memory controller transitions the memory system to a low power mode in response to detecting the transaction queue is has remained in the empty state for a predetermined time. In the transition to the low power mode, the memory controller disables oscillation of one or more timing signals required to time data signaling operations within synchronous communication circuits of one or more attached memory devices and also disables one or more power consuming circuits within the synchronous communication circuits of the one or more memory devices.

Abstract: A method for managing a battery to perform a final action, the method includes determining a battery supplying power to an electronic device is discharging and receiving battery specification information for the battery. The method includes receiving environmental condition information for the battery and determining an open circuit voltage for the battery. The method includes determining a base capacity for the battery, a first capacity reduction for the battery based on the battery specification, and a second capacity reduction for the battery based on the environmental condition information. The method includes determining an overall expected capacity for the battery based on the first capacity reduction and the second capacity reduction, where the overall expected capacity represents available energy. Responsive to determining the available energy for the battery is less than a required energy to perform an action prior to battery depletion, the method includes sending a warning notification.

Abstract: An integrated circuit (IC) device includes a non-volatile memory device with an array of non-volatile memory cells, and an isolation circuit configured to conduct voltage from an internal voltage supply to one of the memory cells during a hidden write operation to the one of the memory cells, and conduct voltage from an external voltage supply to the one of the memory cells during a non-hidden write operation to the one of the memory cells. Current at the external voltage supply can be monitored external to the IC device during the non-hidden write operation, and current of the internal voltage supply is provided by a capacitor that cannot be monitored external to the IC device during the hidden write operation.

Abstract: A multi-die processor semiconductor package includes a first base integrated circuit (IC) die configured to provide, based at least in part on an indication of a configuration of a first plurality of compute dies 3D stacked on top of the first base IC die, a unique power domain to each of the first plurality of compute dies. In some embodiments, the semiconductor package also includes a second base IC die including a second plurality of compute dies 3D stacked on top of the second base IC die and an interconnect communicably coupling the first base IC die to the second base IC die.

Abstract: A main circuit includes a switching element, and converts electric power input to the main circuit and supplies a result of the conversion to a load. The controller switches a control scheme of the main circuit from a first control scheme to a second control scheme at a first time point when the output value starts to vary and switches the control scheme of the main circuit from the second control scheme to the first control scheme at a second time point when a determination is made that switching of a variation direction of the output value will occur on the basis of a detection value of the detector.

Abstract: An audio activity detector device is disclosed. The audio activity detector device comprises a closed loop feedback regulating circuit that supplies an input signal representative of a time-varying voltage signal to a quantizer circuit, wherein the quantizer circuit, as a function of the input signal, converts the input signal to a quantizer discrete-time signal; a first circuit that, as a function of the discrete-time signal, determines a key quantizer statistic value for the quantizer discrete-time signal; and a second circuit that, as a function of the key quantizer statistic value, determines a signal statistic value for the input signal and a gain control value.

Abstract: A computing device apparatus facilitates use of a deep low power mode that includes powering off the device's CPU by including a hardware implemented process to trigger storage of data from the device's volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

Abstract: A power management subsystem included in a computer system may include a host device and a power circuit group. The power circuit group includes multiple power circuits arranged in a tree-like structure. The resources of the multiple power circuits are mapped to corresponding addresses within a common address space. The host device sends, via a first communication bus, commands to a branch power circuit of the multiple power circuits, which, in turn, relays the commands, using a second communication bus, to corresponding ones of the other power circuits based on respective power resources specified in the commands received from the host device.

Abstract: An embodiment of the present invention provides a load sharing control device included in each of multiple power supply devices connected to a load in parallel, the load sharing control device comprising: a first control unit for generating a first control signal which controls an output current of a power supply device, by using the output current of the power supply device and a current of a load share bus; and a second control unit for generating a second control signal which controls an output voltage of the power supply device, by using a target voltage of the power supply device, a feedback voltage received as feedback from the output voltage of the power supply device, and a control voltage according to the first control signal of the first control unit, wherein the first control unit generates the first control signal so that the output current is identical to the current of the load share bus, and limits the output current to a threshold current or less.

Abstract: A method for evaluating metrics associated with isolated execution environments utilized for synthetic monitoring of a web application and modifying the quantity of isolation execution environments hosted by a particular hosting service at a particular geographic location based on the metrics. The method can include receiving an instruction to monitor computing resources at the particular geographic location; obtaining configuration data for the particular geographic location; communicating a request to the particular hosting provider for an identification of a collection of isolated execution environments that are instantiated at the particular geographic location; obtaining metrics associated with the collection of isolated execution environments; evaluating the metrics against the set of scaling criteria; and/or generating an instruction for the particular hosting provider to modify the quantity of the collection of isolated execution environments.

Abstract: A method includes receiving data characterizing a time-dependent first sensor data detected by a first sensor, a time-dependent second sensor data detected by a second sensor, a time-dependent third sensor data detected by a third sensor, a first set of threshold values associated with the first sensor, a second set of threshold values associated with the second sensor, and a third set of threshold values associated with the third sensor and a time window. The first, second, and third sensors are located in a first space of a building. The method further includes calculating a first performance index, a second performance index, and a third performance index. The method also includes classifying the first performance index, the second performance index, and the third performance index into one of a plurality of performance indicators. The method further includes assigning a performance rating score for a space based on the classification.

Abstract: Methods, apparatus, systems, and articles of manufacture are disclosed. In one example, a compute device to manage energy usage and compute performance includes at least one memory, instructions, and processor circuitry. The processor circuitry executes the instructions to determine a system power mode based on first telemetry data associated with the compute device. The processor circuitry executes the instructions to provide user activity data and second telemetry data associated with the compute device to a classification system. The processor circuitry executes the instructions to configure a plurality of parameters to manage power consumption and performance of the compute device based on a classification by the classification system.

Abstract: A seismic sensor assembly can include a housing that defines a longitudinal axis; a sensor; sensor circuitry operatively coupled to the sensor; and overvoltage protection circuitry electrically coupled to the housing.

Abstract: A computing-in-memory apparatus is provided, which includes a voltage regulator having an amplifier and a reference current source, a computing-in-memory array having a plurality of computing units and a detection circuit connected to each other. The amplifier has a current input and a voltage output and is connected to the reference current source, and the voltage regulator provides an output voltage for supplying to the computing-in-memory array. An output current of the detection circuit is inputted into the voltage regulator to compare with the reference current source of the voltage regulator, and then a negative feedback convergence or a negative feedback mechanism is executed according to the comparison result to regulate the output voltage supplied by the voltage regulator to the computing-in-memory array.

Abstract: A computing device is provided, including a battery, a processor configured to receive electrical power from the battery via a voltage regulator, and one or more additional electronic components configured to receive electrical power from the battery. The computing device may further include a first current detector configured to detect a total battery discharge current. The voltage regulator may be configured to receive a first analog current signal from the first current detector, convert the first analog current signal into first digital current data, and transmit the first digital current data to the processor. The processor may be further configured to determine a difference between the total battery discharge current and an available electric current limit for the battery. In response to at least determining the difference, the processor may be further configured to adjust one or more performance parameters of the processor such that the difference is reduced.

Abstract: A processing device of a memory sub-system is configured to sort a plurality of blocks of the memory device; identify, based on scanning of a first block at a first location of the plurality of sorted block, a first voltage bin associated with the first block; identify, based on scanning of a second block at a second location of the plurality of sorted blocks, a second voltage bin associated with the second block; and responsive to determining that the first voltage bin matches the second voltage bin, assign the first voltage bin to each block that is located between the first location of the plurality of sorted blocks and the second location of the plurality of sorted blocks.

Abstract: An information handling system includes a Unified Extensible Firmware Interface (UEFI) and a management controller. The management controller establishes a communication channel with the UEFI, and provides a memory path associated with a driver associated with an operation to be performed in the UEFI. Based on the memory path, the UEFI receives the requested driver from a memory associated with the UEFI, and loads the requested driver. The UEFI executes the loaded requested driver, and provides an execution status for executed driver to the management controller.

Abstract: A method of controlling a microgrid comprises receiving, by a power management system, PMS, of the microgrid, operating point values for a plurality of controllable assets. The method comprises determining, by the PMS, an asset headroom. The method comprises determining, by the PMS, a modified operating point value that is dependent on the received operating point value of the controllable asset, the determined asset headroom of the controllable asset, and a total power offset of the microgrid. The method comprises controlling, by the PMS, the controllable assets for which the modified operating point values have been determined in accordance with the modified operating point values.

Abstract: A power supply system includes an output terminal, a power supply control chip, a power supply switch and a detection device. The power supply control chip is configured to adjust the amount of an input power providing to an electronic device by the power supply device. The power supply switch is configured to control the connection between the power supply device and the power supply control chip. The detection device is configured to detect whether the power supply control chip operates normally. When the power supply control chip operates abnormally, the detection device controls the connection between the power supply device and the power supply control chip through the power supply switch for restarting the power supply control chip. The power supply control chip, the power supply switch and the detection device are disposed in an enclosed space.

Abstract: Memory devices, systems including memory devices, and methods of operating memory devices and systems in which a memory device can include a voltage regulator for adjusting a supply voltage to an output voltage and providing the output voltage to other devices external to the memory device (e.g., other memory devices in the same memory system, processors, graphics chipsets, other logic circuits, expansion cards, etc.). A memory device may comprise one or more external inputs configured to receive a supply voltage having a first voltage level; a voltage regulator configured to receive the supply voltage from the one or more external inputs and to output an output voltage having a second voltage level different from the first voltage level; one or more memories configured to receive the output voltage from the voltage regulator; and one or more external outputs configured to supply the output voltage to one or more connected devices.

Abstract: Techniques discussed herein can facilitate power management at a User Equipment (UE) via selection of a power management stage based on a current power status. One example aspect is a UE comprising one or more processors configured to: monitor a temperature of the UE via one or more temperature sensors and a power usage of the UE; determine a power status of the UE based at least in part on the temperature of the UE and the power usage of the UE; select, based at least in part on the determined power status, a power management stage of a plurality of power management stages; and implement one or more power management techniques associated with the selected power management stage. A notification can be triggered to alert a user that the processor is implementing the one or more power management techniques prior to implementation.

Abstract: A system for consistently implementing reset and power management of IP agents on a System on a Chip (SoC). When IP agents undergo a reset, an individual negotiation takes placed between an interconnect and each IP agent over a link. Each IP agent can emerge from reset at its own time schedule, independently of the timing of the other IP agents. The interconnect may be configured as a proxy for any IP agent that is inoperable, including prior to reset, when in a power-down mode, or malfunctioning.

Abstract: A method of power management for a hub having a plurality of Universal Serial Bus (USB)-C ports includes: allocating a guaranteed power budget to each USB-C port of the hub, wherein one of the USB-C ports has a higher power priority and the other USB-C ports have a lower power priority; reducing the guaranteed power budget allocated to a USB-C port with the lower power priority if measured power for that USB-C port is below its currently guaranteed power budget by a predetermined amount; and offering additional power budget to the USB-C port with the higher power priority if the guaranteed power budget allocated to a USB-C port with the lower power priority was previously reduced. Corresponding USB-Power Delivery (PD) integrated circuit (IC) controllers and hubs are also described.

Abstract: A system and/or method can include power of Ethernet (PoE) controller including a PoE interface, a device interface and a controller, communicatively coupled to the PoE interface and the device interface. The controller can be configured to receive device control information via the PoE interface and to generate control instructions in response to the device control information for the device interface.

Abstract: Systems and devices are provided to increase computational and/or power efficiency for one or more neural networks via a computationally driven closed-loop dynamic clock control. A clock frequency control word is generated based on information indicative of a current frame execution rate of a processing task of the neural network and a reference clock signal. A clock generator generates the clock signal of neural network based on the clock frequency control word. A reference frequency may be used to generate the clock frequency control word, and the reference frequency may be based on information indicative of a sparsity of data of a training frame.