Patents Represented by Attorney, Agent or Law Firm A. Sidney Johnston
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Patent number: 6256323Abstract: Method of processing asynchronous characters in order to transmit them over an ATM network (10, 12 or 16) of a communication system having a first endpoint (36) and a second endpoint (38), a first group of one or more Data Terminal Equipments (DTE) being connected to the first endpoint and a second group of one or more DTE's being connected to the second endpoint and wherein data are transmitted from the first group of DTE's to the second group of DTE's by the intermediary of the ATM network. Asynchronous characters are processed as they are received at the first endpoint from the first group of DTE's by removing Start, Stop and parity bits. A block is generated consisting of one or more processed asynchronous characters received in sequence from a particular DTE of the first group of DTE's. An ID byte is added to the block to identify the transmitting DTE, yielding a data unit. A plurality of such data units are concatenated to build a data unit frame.Type: GrantFiled: March 31, 1998Date of Patent: July 3, 2001Assignee: Cisco Technology, Inc.Inventors: Alain Benayoun, Patrick Michel, Maurice Duault, Jean-Francois Le Pennec
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Patent number: 6249818Abstract: Application programs can dynamically link to multiple transports by attaching and detaching vectors (jump addresses, i.e., entry points to the functions provided by third party transport stack/drivers) of third party transport stack/drivers in a dynamic manner. Notify callbacks are made from the transport stack/driver, allowing asynchronous operation without requiring the application to wait for the transport stack/driver to confirm a network transport operation.Type: GrantFiled: June 30, 1993Date of Patent: June 19, 2001Assignee: Compaq Computer CorporationInventor: Dushyant Sharma
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Patent number: 6246669Abstract: In a high speed digital network including access nodes and network nodes each having topology data bases, a method for optimizing the connection set-up operations required for connecting a calling end-user attached to a local access node to a destination user attached to a remote access node, via a conventional connection set-up operation. An Access Node Connection Table (ANCT) in each access node stores a list of every remote access node for which the local access node has at least one user connection. A field in the locate reply message is defined for the destination remote Access Node Topology Database (ANTDB) and remote ANTDB information is inserted prior to sending the reply message. Locate reply message reception is monitored by the local access node, and upon reception an entry is created for the received remote ANTDB information in the local access node unless the remote access node was already identified in the local access node. An optimal path is then selected and connection set up.Type: GrantFiled: November 17, 1998Date of Patent: June 12, 2001Assignee: Cisco Technology, Inc.Inventors: Denis Jean Albert Chevalier, Philippe Michel Bazot, Olivier Maurel, Eric Levy-Abegnoli, Olivier Bertin, Laurent Nicolas, Jean-Paul Chobert
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Patent number: 6243275Abstract: A full bridge and half bridge dc-dc converter including a primary side having switching devices connected to a transformer, and a primary side controller, a secondary side including switching devices connected to a secondary side of the transformer, an inductor, and secondary side controller, a central control synchronizing the primary side controller and the secondary side controller, and a set of rules for controlling the primary side and secondary side switches such that a utilization rate exceeds fifty percent.Type: GrantFiled: September 28, 1999Date of Patent: June 5, 2001Assignee: Galaxy Power, Inc.Inventor: Andrew Ferencz
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Patent number: 6236658Abstract: In a router coupled to a number of networks, a data packet is received from a first one of the networks and routed to a second one of the networks. The data packet includes a first portion having a destination network address. The destination network address for the data packet is input to a content addressable memory (“CAM”) while the router is still receiving at least a portion of the data packet, so that the CAM, having network address information stored therein, identifies one of the networks coupled to the router and corresponding to the destination address of the data packet while the router is still receiving at least a portion of the data packet.Type: GrantFiled: November 21, 1997Date of Patent: May 22, 2001Assignee: Cisco Technology, Inc.Inventors: Alexander Dankwart Essbaum, Aubrey Deene Ogden
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Patent number: 6226409Abstract: The invention recognizes that a probability density function for fitting a model to a complex set of data often has multiple modes, each mode representing a reasonably probable state of the model when compared with the data. Particularly, an image may require a complex sequence of analyses in order for a pattern embedded in the image to be ascertained. Computation of the probability density function of the model state involves two main stages: (1) state prediction, in which the prior probability distribution is generated from information known prior to the availability of the data, and (2) state update, in which the posterior probability distribution is formed by updating the prior distribution with information obtained from observing the data. In particular this information obtained purely from data observations can also be expressed as a probability density function, known as the likelihood function.Type: GrantFiled: November 3, 1998Date of Patent: May 1, 2001Assignee: Compaq Computer CorporationInventors: Tat-Jen Cham, James Matthew Rehg
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Patent number: 6219416Abstract: A FISU frame handler which is connected between an adapter and a SS7 low speed network. For each FISU frames transmitted or received in the adapter, an interrupt is generated to a processor located in the adapter. In order to diminish the number of processor interruptions, the FISU frames are externally processed by the FISU frame handler by discarding repeated FISU frames transmitted from the network so as to generate idle state signals to the adapter and by converting idle state signals received from the adapter into repetitive FISU frames to transmit them to the network without interrupting the processor. In order to perform both functions, the FISU frame handler comprises two dedicated hardware units which operate according to specific methods.Type: GrantFiled: February 27, 1997Date of Patent: April 17, 2001Assignee: Cisco Technology, Inc.Inventors: Alain Benayoun, Jean-Francois Le Pennec, Patrick Michel, Claude Pin
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Patent number: 6097882Abstract: A client-server network including a number of client computer systems, each of the client computer systems having a network interface, a number of server computer systems, each of the server computer systems having a network interface, and a replicator system connecting the client computer systems to the server computer systems, the replicator system transparently processing a number of requests from the client systems to a number of services resident in the server systems.Type: GrantFiled: June 30, 1995Date of Patent: August 1, 2000Assignee: Digital Equipment CorporationInventor: Jeffrey C. Mogul
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Patent number: 5819282Abstract: A data base is created by storing a plurality of data objects in a memory. Each data object has attributes including a key value and a data value. The data objects are partitioned into a plurality of classes, each class having one or more members, each member including the same attributes of the data objects. An access method is defined for at least one member of a specific class to access the data objects of the specific class by key values. For another member of the specific class, an access method to access the data objects of a related class is defined. A specific data value of a specific data object is compared with the key values of the data objects of the related class, and if the specific data value is equal to the key value of a related data object a memory address of the related data object is associated with the specific data value.Type: GrantFiled: July 17, 1996Date of Patent: October 6, 1998Assignee: Digital Equipment CorporationInventors: Donald F. Hooper, Jay S. Newcomb
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Patent number: 5814762Abstract: An apparatus is provided to reduce the amount of EMI generated by a circuit. The grounding of an enclosure is improved by providing a number of shaped protuberances, the protuberances having an end that penetrates a conductive region of a circuit board, such that when the circuit board is mounted to the support member, the protuberances make a penetrating electrical contact and provides for additional ground paths, thereby reducing the EMI generated by the assembly.Type: GrantFiled: July 25, 1996Date of Patent: September 29, 1998Assignee: Digital Equipment CorporationInventors: Ralph Michael Tusler, Mark S. Lewis, Reuben Martinez
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Patent number: 5805808Abstract: A parser for reading bits of a packet has a set of logic circuits implemented in a computer chip; a memory interacting with the computer chip, the memory providing first data to the set of logic circuits; means for reading bits from any field of packet into the set of logic circuits, the bits providing second data to the set of logic circuits; means, responsive to the first data and the second data, for the logic circuits to interpret bits of the packet.Type: GrantFiled: April 9, 1997Date of Patent: September 8, 1998Assignee: Digital Equipment CorporationInventors: Santosh K. Hasani, Satish L. Rege, Mark F. Kempf
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Patent number: 5787465Abstract: A hierarchical memory arrangement for use with a processor includes a cache, addressable by source addresses, and a set of processor registers, addressable by destination addresses. For each processor register there is a miss status holding registers. If the cache does not store data requested for one of the processor registers, a miss condition is generated. In response to the miss condition, the address of a cache block to contain the missing data is stored in the miss status holding register corresponding to the processor register for which the data are requested. While the requested data are transferred from a main memory to the cache, the cache is not locked up and additional data accesses are allowed.Type: GrantFiled: August 21, 1996Date of Patent: July 28, 1998Assignee: Digital Equipment CorporationInventors: Norman P. Jouppi, Ramsey W. Haddad
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Patent number: 5783771Abstract: The invention relates to an enclosure for computers that is formed by slidably joining together two chassis portions. A groove formed in a wall of one chassis portion mates with a tongue formed in a wall of the other chassis portion. The tongue enters one end of the groove and slides throughout the groove's length until the two chassis portions become fully joined and form a completed enclosure. The combination of the tongue and groove forms a slidable tongue and groove joint. When both chassis portions are made of electrically conductive material, the tongue and groove joint effectively inhibits the passage of electromagnetic radiation through the seam that forms at the juncture of the two chassis portions.Type: GrantFiled: October 6, 1995Date of Patent: July 21, 1998Assignee: Digital Equipment CorporationInventors: Jeffrey P. Copeland, Dennis C. Robinson
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Patent number: 5761427Abstract: In an asynchronous transfer network (ATM), to prevent the bottleneck associated with a host central processing unit (CPU) trying to receive status information for a plurality of interrupts occurring over an interface input/output (I/O) bus, a method and apparatus which transfers all status information directly to the host memory without host involvement. The host CPU is then notified of this new status information via an interrupt. When status information is transferred to the host memory, consistency is ensured and the number of spurious interrupts are reduced. A host software driver may then read the latest status information from the interface I/O bus at its convenience any not incur any performance penalties of I/O accesses.Type: GrantFiled: July 14, 1997Date of Patent: June 2, 1998Assignee: Digital Equipment CorporationInventors: Bhupendra Shah, Peter J. Roman, Michael Ben-Nun, Kadangode K. Ramakrishnan
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Patent number: 5752255Abstract: A dynamic cache resizing mechanism permitting a non-coherent cache memory to be altered in size during the operation thereof. A cache utilization monitoring system determines whether the cache size is optimised for a particular application and environment, and if it is not, modifies a selection process to resize the cache address space. The non-coherent property of the cache is utilized to permit the change of selection process during use, and the choice of selection process may be effected to take into account the proportion of live cache entries which will remain accessible after resizing, and the proportional change in size of the cache during a resizing operation.Type: GrantFiled: February 3, 1997Date of Patent: May 12, 1998Assignee: Digital Equipment CorporationInventor: Neil Alasdair James Jarvis
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Patent number: 5748961Abstract: A software system is defined by a tree of system models which are written in a functional language. During a build of the software system, the functions are interpreted and the results of the expensive expressions are cached. Each function is examined before interpretation to see if it has been evaluated before. If a function has already been evaluated, the cached result is retrieved by the evaluator and the time which would have been spent re-evaluating the function is saved.Type: GrantFiled: August 30, 1996Date of Patent: May 5, 1998Assignee: Digital Equipment CorporationInventors: Christine Beth Hanna, Roy Levin
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Patent number: 5745697Abstract: A computational method and apparatus allocates transmission rate to source end nodes, and both reduces the computational complexity, and reduces the state information which must be retained concerning each VC, without significantly degrading convergence properties for the network. Also, the computational method is useful with either interval based or proportional schemes of flow control. A plurality of virtual circuits is established between source end stations and destination end stations, the plurality of virtual circuits passing through an intermediate node. The source end stations transmit data packets at a plurality of discrete transmission rates. The intermediate node counts the number of virtual circuits using each of the discrete transmission rates. The intermediate node maintains an indication that a select virtual circuit has been counted in the step above, and does not count the virtual circuit more than once during a switch time interval.Type: GrantFiled: March 27, 1996Date of Patent: April 28, 1998Assignee: Digital Equipment CorporationInventors: Anna Charny, K. K. Ramakrishnan
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Patent number: 5734659Abstract: A system has a node connected to a network, the node generating a separate session message for each of a plurality of users. The node places each of the separate session message in a slot in a single virtual circuit message, and transmits the virtual circuit message onto the network. A server is connected to the network, and the server receives the virtual circuit message, and the server identifies each of the separate session messages. The server then transmits each of the separate session message to a user having a session corresponding to each of the separate session messages.Type: GrantFiled: April 1, 1994Date of Patent: March 31, 1998Assignee: Digital Equipment CorporationInventors: Bruce Mann, Darrell Duffy, Anthony Lauck, William Strecker
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Patent number: 5734825Abstract: A rate based, end to end flow control system is disclosed for a communications network. The disclosed rate based flow control system includes each source end station selecting its transmission rate from a set of permitted discrete transmission rates. The set of permitted discrete transmission rates is based on a logarithmic encoding. The disclosed rate based traffic control system further requires each source end station to send one end to end control cell every time period T. The time period T is also known by switches in the communications network, and is used to periodically calculate an available allocation (or "fair share") of bandwidth at a switch for a given virtual circuit.Type: GrantFiled: July 18, 1994Date of Patent: March 31, 1998Assignee: Digital Equipment CorporationInventors: Anthony G. Lauck, Anna Charny, Kadangode K. Ramakrishnan
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Patent number: 5717575Abstract: This invention is a system for self guiding interengagement of a securement member within a mating member having a slot for holding and securing two surface areas. The securement member is attached to one surface area and the mating member is attached to the other surface area. The securement member has a shape and the mating member has a tongue with a guiding surface, thereby promoting self guiding interengagement of the securement member within the slot of the mating member. The system is convenient for inserting a board within the obstructed view of a receptacle, such as a computer enclosure.Type: GrantFiled: August 9, 1995Date of Patent: February 10, 1998Assignee: Digital Equipment CorporationInventors: Jeffrey P. Copeland, Dennis Robinson