Abstract: An analog-to-digital converter device capable of measuring inputs beyond a supply voltage including: an N bit analog-to-digital converter powered by a supply voltage and a reference voltage; a range resolution stage capable of receiving inputs at higher voltages than the supply voltage, providing an input to the analog-to-digital converter, and outputting a logic value of one for the N+1th bit in response to an input signal higher than the reference voltage; and a bootstrapped input multiplexer stage for connecting low voltage input signals directly to the analog-to-digital converter and for connecting input signals that can exceed the supply voltage to the range resolution stage.

Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Abstract: A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for each transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived form the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.

Abstract: The image sensing device provides a digital output for each pixel. As charge builds up in a pixel, the pixel output increases until it reaches a reference level. When the reference level is crossed the pixel is reset. This process is repeated several times in a given frame time cycle with the reference level steadily decreasing. The various reset times represent the light intensity on the pixel. For an image sensor array, the array is scanned multiple times during one image frame time cycle and the reference level is lowered each scan. This provides an image sensor that has built-in pixel non-uniformity suppression, digital output, and high sensitivity.

Abstract: A low power bus hold circuit includes: a first inverter having an input coupled to a bus hold input node; and a second inverter having a first input coupled to a first output of the first inverter and a second input coupled to a second output of the first inverter, wherein the first and second outputs of the first inverter are separated by a resistor, and having an output coupled to the bus hold input node.

Abstract: A self-clocking memory device comprises a memory array, a memory input circuit, and a memory control circuit. The memory input circuit is operable to receive an input clock signal and generate a memory operation initiation signal in response thereto, while the memory control circuit is operable to receive the memory operation initiation signal and generate one or more control signals to initiate a memory operation in response thereto. The memory control circuit is further operable to identify completion of the memory operation and generate a cycle ready strobe signal in response thereto. The memory input circuit receives the cycle ready strobe signal as an input and generates a next memory operation initiation signal in response thereto for initiation of a next memory operation.

Abstract: Reducing the effect of coupling on a reference voltage received at a node of an output buffer, wherein the effect of coupling is due to the transitions in the output signals. An inverted signal of the output signal is connected to the node through an impedance (e.g., capacitor) that stores energy. The inverted signal pulls the node in the opposite voltage level direction compared to the coupling effect of the output signal, thereby leaving the reference voltage substantially unchanged. By selecting the capacitance of the capacitor equaling the parasitic capacitance between the node and the output of the output buffer, coupling may be reduced substantially.

Abstract: The low AC impedance input stage circuit for fast startup applications includes: a first transistor coupled between a first input node and a first output node; a second transistor coupled between a second input node and a second output node, and having a control node coupled to a control node of the first transistor; a third transistor coupled to the first input node and having a control node coupled to the control node of the first transistor; a fourth transistor coupled to the second input node and having a control node coupled to the control node of the third transistor; a first blocking device coupled between the third transistor and a first current source; a second blocking device coupled between the fourth transistor and the first current source; and a bias device coupled between the first current source and the control node of the first transistor.

Abstract: The load limit on each path to avoid EM is estimated and provided as an input to various early design stages (such as placement and routing). Each (of one or more) of the early stages may ensure that the load limit is not violated. Techniques such as increasing the path width and inserting additional circuit (e.g., a buffer cell) in the path, may be employed to avoid the EM violations. As a result, unneeded iterations of design stages may be avoided for purposes of EM checks alone.

Abstract: Electrostatic discharge protection circuitry includes a timing circuit operably coupled between the high supply side and low supply side of an associated circuit. The timing circuit has an RC node used for triggering a series of inverters configured to control an ESD dissipation device operably coupled to the high supply side node and the low side supply node of the circuit. A feedback transistor network and a feedback conditioning network is provided for ensuring that the ESD device is held on during an ESD event.

Abstract: A CCD device incorporates Charge Multiplication in its CCD registers together with charge domain Dynamic Range compression. This structure preserves the high dynamic range available in the charge domain of these devices, and avoids limiting it by an inadequate voltage swing of the charge detection nodes and amplifiers. The Dynamic Range compression is logarithmic from a predetermined built in threshold and noiseless. The technique has an additional advantage of maintaining the compact size of the registers, and the registers may also include antiblooming devices to prevent blooming.

Abstract: The CML (current mode logic) to CMOS converter with a leakage balancing transistor for jitter reduction includes: a differential input stage; an output stage having a first branch coupled to a first output of the differential input stage and a second branch coupled to a second output of the differential input stage; and a leakage balancing transistor coupled to the first branch of the output stage.

Abstract: A bootstrapping circuit capable of sampling inputs beyond a supply voltage which includes a bootstrapped switch coupled between an input node and an output node, a first transistor having a first end coupled to a control node of the bootstrapped switch, a first capacitor having a first end coupled to a second end of the first transistor, a second transistor coupled between the first end of the first transistor and a supply node, and having a control node coupled to a first clock signal node, a third transistor coupled between the second end of the first transistor and the supply node, a charge pump having an output coupled to a control node of the third transistor, a level shifter having an output coupled to a second end of the first capacitor, a fourth transistor cross-coupled with, the first transistor, a fifth transistor having a second end coupled to the first end of the fourth transistor, and having a control node coupled to the output of the level shifter, and a sixth transistor coupled between the firs

Abstract: Disclosed are integrated circuits having multiple electromagnetically emissive devices, such as LC oscillators. The devices are formed on an integrated circuit substrate and are given different planar orientations from each other. Particular integrated circuit packages disclosed are “flip-chip” packages, in which solder bumps are provided on the integrated circuit substrate for flipping and mounting of the finished integrated circuit upon a printed circuit board or other substrate. The solder bumps provide conductive connections between the integrated circuit and the substrate. The orientations and positioning of the emissive devices are such that one or more of the solder bumps are interposed between neighboring emissive devices to act as an electromagnetic shield between them.

Abstract: A circuit for receiving multiple serial datastreams in parallel is disclosed. A bit clock is recovered from each data stream, there being one data bit for each transition of the clock signal both positive and negative going. The phases of the bit clocks are compared and are adjusted by 180 degrees so that the positive going edges of all occur close to each other. The bits of each stream are assembled into words under the control of a word clock. In one embodiment a common word clock is derived form the set of bit clocks as a whole. In another embodiment each stream is provided with its own word clock which is aligned to positive edges of the respective bit clocks that are close to each other.

Abstract: A technique to enhance performance and reduce silicon area for a TCAM system which includes a plurality of CAM blocks that are organized into at least one rectangular array having rows each having a plurality of CAM blocks, a group of TCAM cells and associated read/write bit lines connecting the group of CAM cells to search bit lines. Each TCAM cell in the TCAM architecture includes a pair of memory elements that is connected to a pair of associated compare circuits such that the interconnections between the memory elements and the compare circuits are substantially vertical in active MOS layers and substantially horizontal in the metal layers to facilitate sharing of adjacent cells thereby providing reduced silicon area and a short aspect ratio.

Abstract: The present invention achieves technical advantages as a high performance analog charge pumped phase locked loop (PLL)(10) with process and temperature compensation in closed loop bandwidth. The PLL reduces the variation in bandwidth and stability by making the product KVCO*ICP independent of process and temperature variation. The PLL achieves a higher performance than existing PLL architectures, achieving a high dynamic range up to at least 110 dB, such that a PWM class-D amplifier is realizable with this PLL. The PLL has a constant bandwidth and damping factor while using an analog charge pump (16).

Abstract: The voltage tolerant circuit with improved latchup suppression includes: a diode device having a first end coupled to a source voltage node; a first NWELL guard ring surrounding the diode device; a diode coupled between a second end of the string of diodes and an output pad; a second NWELL guard ring surrounding the diode; and a transistor device coupled between the output pad and a substrate node. The NWELL guardrings disrupt the parasitic SCR operation by adding an additional N+ diffusion without affecting the substrate pump current delivered by the diode.

Abstract: The charge pump circuit includes: a charge pump output branch; a current leakage device coupled to the output branch; and a feedback device coupled between the output branch and a control node of the current leakage device such that the leakage device cancels leakage current from the output branch.

Abstract: A low power E-fuse repair methodology substantially removes system latency during memory and/or E-fuse farm module power-down in a device that employs E-fuse farm technology. The method maintains power to the repair registers and minimal control logic in the memories, while all other circuitry can be either placed in a low power data retention mode, or completely powered off. There is no need to rescan the repair data from the E-fuse farm after one or more memories are powered back up. This provides dynamic power savings since there is no longer any need to idle the system to reload repair data. Since the E-fuse farm can be powered down after initial system power-up and repair data is loaded into the memories, there is also a significant leakage power savings.