Abstract: A method of communicating is disclosed in which the receiving device acknowledges the receipt of a valid transmission and awaits the receipt of an abort message from the transmitting device before accepting the transmitted data. The transmitting device awaits the receipt of a valid acknowledgement and, if it fails to receive such an acknowledgement within a predetermined time-period, transmits an abort message to the receiving device. In multinodal, peer network communication systems, the acknowledgement and abort message may be transmitted during brief, dedicated time-periods following the transmission of data.

Abstract: Incoming data messages to a system having a plurality of channels are assigned for processing to one of the channels to share the processing load more or less equally among all the channels of the system. Each channel receives messages by means of a communications link for processing. Included in each channel is a disk drive for a storage medium, a disk controller and peripheral controllers for input/output equipment as required. Each channel of the system also includes a data processor. A message is received from the communication link of any of the channels, which message is identified by the data processor of that channel. The processor then evaluates the number of messages waiting to be processed in each of the other channels for assignment to a channel having the least number of messages on the processing list. The processor considers only on-line channels in this assignment selection.

Abstract: A digital programmable packet switch synchronizer receives a digital input data stream which includes a unique digital word. The unique digital word is stored in the synchronizer in a random access memory. A group of the most recently received data bits are stored in memory along with a blanker bit for each data bit. The blanker bit determines the valid or invalid status of the data bit. During each bit period of the incoming data stream, the stored data bits are serially compared with the stored unique word. A count is made of the number of noncomparisons between the stored data bits and the stored unique word bits when the data bit is valid. If the number of noncomparisons does not exceed a programmed error limit, an output signal is generated to indicate detection of the unique word. A similar count is carried out for detection of the inverse to the unique word.

Abstract: A multinodal data communication network permits the sharing of remote resources by a wide variety of computing devices. Data or messages generated at one device may be sent to any or all the other devices sharing a common transmission medium. Message handling capability of the network is increased by the use of a plurality of transmission media connected to the computing devices through interface stages. Both priority message transmission and improved acknowledgement protocols are implemented.

Abstract: A leading edge estimator for a vehicle terrain navigation system is described, the system having a radar terrain sensor which generates a position signal. The leading edge estimator includes a storage circuit for storing a time of arrival signal estimate. A delay circuit receives the position signal from the radar terrain sensor and produces a delayed version thereof. The position signal and the delayed version thereof are differenced and applied to a sample & hold circuit, which generates a sample of the differenced signal after a predetermined time period. The output of the sample & hold circuit is then applied to a one bit analog-to-digital convertor which determines the sign of the sampled difference signal. The output of the analog-to-digital convertor is then used as a control signal to effect the gating of one of two predetermined weighting factors.

Abstract: A detector (20) is provided for use in a communication receiver where a received spread spectrum data signal is detected using a locally generated reference signal to decode the data signal. The detector (20) includes first (22) and second channels (24) and circuitry (90) for applying the received encoded data signal to the first (22) and second channels (24). A local generator (50) is provided for generating the reference signal wherein the reference signal has polarity transitions. A demodulator (40) is included in the first channel (22) for generating a detected recovered data signal from the received data signal in response to the reference signal. Circuitry (52) is provided for detecting the polarity transitions in the reference signal and for generating a differential PN signal. Circuitry (42) is further provided in the second channel (24) for correlating the received data signal and the differential PN signal to thereby generate a recovered error signal.

Abstract: A method of communicating is disclosed in which the receiving device acknowledges the receipt of a valid transmission and awaits the receipt of an abort message from the transmitting device before accepting the transmitted data. The transmitting device awaits the receipt of a valid acknowledgment and, if it fails to receive such an acknowledgment within a predetermined time-period, transmits an abort message to the receiving device. In multinodal, peer network communication systems, the acknowledgment and abort message may be transmitted during brief, dedicated time-periods following the transmission of data.

Abstract: A method and apparatus for baseband synchronizing of a local PN code sequence with a received PN code sequence incorporated in a received spread spectrum signal is provided. The received spread spectrum signal is translated to baseband to produce an I (in-phase) channel baseband signal and a Q (quadrature-phase) channel baseband signal. Data and error baseband correlators correlate the I channel and Q channel baseband signals with in-phase and quadrature-phase PN signals incorporating the local PN code sequence to produce despread on-time, advanced and delayed I channel and Q channel baseband signals. These despread baseband signals are processed and combined to produce an error signal proportional to a difference between the local PN code sequence and the received PN code sequence. A numerically-controlled oscillator circuit is responsive to the error signal to advance or delay the phase of a reference PN clock signal used to form a local PN clock signal.

Abstract: A method and apparatus for baseband generation of a spread spectrum reference signal for an LMS adaptive array processor is provided. An IF summed, weighted spread spectrum signal is output from the processor and translated to baseband to produce an I (in-phase) channel spread baseband signal and a Q channel (quadrature-phase) spread baseband signal. A baseband correlator receives the I channel and Q channel baseband signals and delayed versions of in-phase and quadrature-phase PN signals and produces despread I channel and Q channel baseband output signals. A baseband linear spreader receives the despread I channel and Q channel baseband output signals and the in-phase and quadrature-phase PN signals and produces respread I channel and Q channel baseband signals. A baseband modulator modulates the respread I channel and Q channel baseband signals with a phase-shifted local oscillator to produce the reference signal.

Abstract: Apparatus for determining the position and velocity of a vehicle over a given area as represented by stored data includes a radar terrain sensor responding to radar pulse returns and generating video signals to a terrain clearance estimator. Also input to the terrain clearance estimator are vehicle vertical position data and vertical speed data which along with the video output of the terrain sensor generates by means of a time of arrival estimator observed clearance signals which are sampled and input to a buffer. Also stored in the buffer are vehicle position and velocity signals from an inertial navigation system with the buffer data accessed by an error correction estimator. The error correction estimator responds to stored data to generate a sequence of position and velocity error correction signals each comprising three components.

Abstract: A method and apparatus is disclosed for decoding a redundantly coded digital signal wherein each information character is coded with a plurality of signal elements. Each of the signal elements is sampled by an analog to digital converter (110) and the resulting sample value is transmitted to an adder (114). The sampled value is added to an accumulated sum which is received from a storage circuit (128). The sum of the sampled value and the accumulated sum is transmitted through a selector switch (120) to both a decision circuit (126) and the storage circuit (128). After the last of the redundantly coded signal elements is sampled and the sampled values included within the accumulation sum, the state of the information character is determined by the decision circuit (126). Switch (120) then enters a null data set to reset the accumulated sum to zero for processing the next group of redundantly coded signal elements.

Abstract: A variable threshold receiver is disclosed which compensates for direct current (dc) voltages present in a received signal. The receiver utilizes an integrator-comparator circuit to recover data which may have been distorted by the presence of dc voltages. The integrator-comparator circuit provides data recovery by tracking the average of the peak signal levels of the received signal, eliminating the need for a lengthy preamble to compensate for receiver attack time.

Abstract: A method and apparatus for phase modulating a carrier signal to convey an information signal (12) such that the carrier signal has a constant amplitude envelope. A Hilbert transform signal (14) of the information signal (12) is produced. The signals (12, 14) are sampled to produce signals (16, 18), which represent cartesian coordinate values. The cartesian coordinate values are then converted into equivalent polar vectors (20-36) which have both an amplitude (R) and an angle (.theta.). The polar vector quantity (R, .theta.) is converted into two unity amplitude vectors (A, B). The unity amplitude vectors (A, B) are offset from the polar vector quantity by an angle the cosine of which is proportional to the amplitude of the polar vector (R). The carrier signal is sequentially phase modulated phase angles of the unity amplitude vectors (A, B) for each sample period of the information signal.

Abstract: A modulating circuit (10) receives a UHF carrier signal together with a digital input signal for data along with a data clock. A channelizer circuit (60) produces I and Q channel digital data signals derived from the digital input signal. The I and Q channel signals are utilized to trigger one shot circuits (70, 72, 74 and 76) to produce positive and negative pulses corresponding to the signal transitions of the input signals thereto. These pulse signals are provided to integrate and hold circuits (80, 82) which serve to have positive and negative integration, thereby producing ramp signal segments in place of the sudden transitions of the rectangular digital input signals. The resulting data signals from the integration process are passed through diode shaper circuits (82, 92) and low pass filters (88, 94) to produce spectrum shaped I and Q channel modulating signals which have a limited bandwidth.

Abstract: Apparatus for determining the position and velocity of a vehicle over a given area as represented by stored data includes a radar terrain sensor responding to radar pulse returns and generating video signals to a terrain clearance estimator. Also input to the terrain clearance estimator are vehicle vertical position data and vertical speed data which along with the video output of the terrain sensor generates by means of a time of arrival estimator observed clearance signals which are sampled and input to a buffer. Also stored in the buffer are vehicle position and velocity signals from an inertial navigation system with the buffer data accessed by an error correction estimator. The error correction estimator responds to stored data to generate a sequence of position and velocity error correction signals each comprising three components.

Abstract: A method and apparatus for phase modulating a carrier signal to convey an information signal (12) such that the carrier signal has a constant amplitude envelope. A Hilbert transform signal (14) of the information signal (12) is produced. The signals (12, 14) are sampled to produce signals (16, 18), which represent cartesian coordinate values. The cartesian coordinate values are then converted into equivalent polar vectors (20-36) which have both an amplitude (R) and an angle (.theta.). The polar vector quantity (R,.theta.) is converted into two unity amplitude vectors (A, B). The unity amplitude vectors (A, B) are offset from the polar vector quantity by an angle the cosine of which is proportional to the amplitude of the polar vector (R). The carrier signal is sequentially phase modulated by each of the angles of the unity amplitude vectors (A, B) for each sample period of the information signal.

Abstract: A baseband correlation circuit (10) receives an IF spread spectrum input signal which is phase compared with a local oscillator signal and a phase shifted local oscillator signal to produce I channel and Q channel spread baseband signals. Each of these signals is input to four sample and hold circuits (34-48). A local PN code signal is converted from two-phase to four-phase to produce I and Q channel local PN signals. These signals together with the logical inverses thereof are provided as the control inputs for the sample and hold circuits (34-48). For each pair of sample and hold circuits there is a respective summer (86-92). The pair of sample and hold circuits together with the corresponding summer comprises a double balanced multiplier. There are four double balanced multipliers for producing four respective product signals. The product signals are input as pairs into summers (106) and (108) to produce despread, narrowband baseband I and Q channel output signals at output lines (110, 112).

Abstract: A detector circuit (10) is programmed to produce an output signal when an input signal is at a predetermined frequency. The input signal is provided to an inverter (14) to produce an inverse signal. The input signal together with the inverse signal are provided to two switches (16, 18). The switches (16, 18) are driven by first and second drive signals produced by a drive generator (60). The output terminals (24, 28) of the switches are alternately connected to the input terminals in synchronism with the corresponding drive signals. The output signals from the switches (16, 18) are transmitted through low pass filters (26, 30) and the resulting signals are combined to produce a summation signal by a summation circuit (36). The summation signal is passed through an absolute value circuit (40) to produce an absolute value signal. The absolute value signal is examined by a threshold detector circuit (44) which produces an output when the absolute value signal exceeds a preset threshold.

Abstract: A frequency synthesizer having a delay line for a controlling element. The output frequency of a voltage controlled oscillator (VCO) is sampled with a directional coupler and input to an in-phase power divider. The first output of the power divider is input to a delay line to provide a delayed signal. The delayed signal and the non-delayed signal from the second output of the power divider are input to a phase detector. The output of the phase detector is a DC voltage representative of the phase difference between the delayed signal and the non-delayed signal. An analog gate inputs the phase detector output to an oscillator driver that controls the VCO. When the phase difference deviates from a predetermined level the oscillator driver outputs an error voltage to adjust the VCO until the proper phase difference is achieved which will be a condition of phase lock wherein the output frequency is phase locked to the delay line.

Abstract: To control the operation of an actuator motor (48) an input signal is compared with a feedback signal at a summing junction (22) with the resultant error signal used to bias off the output of a sawtooth generator (30) by pulse width modulation in a modulator (28). The pulse width modulated signal and three commutation signals from an optical detector (34) are input to a commutation circuit (32) that decodes the input by means of a programmed read only memory into a six state drive voltage that is applied to optical isolators (36), (40) and (44). Two of the six states from the commutation circuit (32) are input to each optical isolator that provides an output for driving a power stage. The optical isolator (36) drives a power stage (38), the optical isolator (40) drives a power stage (42) and the optical isolator (44) drives a power stage (46). Each of the power stages has an output connected to one motor lead for the delta wound motor (48) that includes velocity limit protectors (76) through (78).