Abstract: A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.

Abstract: An early no-overflow signaling system and method is used in conjunction with performing nonrestoring division using two's complement 2n bit dividends N and two's complement n bit divisors D--when a no-overflow condition is signaled, a subsequent plurality of iterative partial remainder computations are performed to obtain the quotient Q and remainder R with no possibility of overflow. Dividends N are characterized by a 2-bit sign field N(s1s2) formed by a first sign bit N(s1) and a second sign bit N(s2), a high order n-1 dividend magnitude bits N(himag), and a low order n-1 dividend magnitude bits N(lomag), such that N(s1) and N(himag) form a 2's complement number N(hi), while divisors D are characterized by a leading sign bit D(s) and n-1 divisor magnitude bits D(mag). Early no-overflow signaling logic uses the input dividend N and divisor D, and a 2n-1 bit first partial remainder (which has a value of [N-2.sup.

Abstract: A procedure for implementing cache line replacement cycle as split replacement cycles is used in a 64/32 computer system including a 64-bit x86 microprocessor interfaced to a 32-bit x86 bus architecture which does not support pipelined bus cycles. The microprocessor includes an internal L1 cache with two sectors S0 and S1 per cache line such that a cache line replacement request involving both sectors is performed as a split replacement cycle with a separate burst write cycle for each sector. The microprocessor's bus interface unit (BIU) includes (a) a BCC register which is used to stage the first sector (S0) of a split replacement cycle as the current bus cycle, and (b) a BNC register, which is used in a pipelined 64-bit bus architecture to stage pipelined bus cycles, but is used in the exemplary 64/32 system to stage the second sector (S1) of the split replacement cycle.

Abstract: A single block bus transfer (SCBT) protocol is implemented, in an exemplary embodiment, in a computer system that includes an .times.86 microprocessor, system logic, and an external memory subsystem including L2 cache and system DRAM, intercoupled by a 586 bus architecture. The microprocessor's bus interface unit (BIU) includes SCBT logic that generates internal effective BRDY# and the effective KEN# signals from either (a) L2.sub.-- HIT from the L2 cache, or (b) BRDY# or KEN# from the system logic. The effective KEN# signal is used for convert a potentially cacheable read into a burst fill cycle. The exemplary L2 cache is able to perform address decode and cache look-up in time to return L2 HIT to the processor during the ADS# clock with sufficient timing margin to permit the processor to complete the bus transfer (either not burst bus cycle, or the first bus transfer of a burst cycle) in that clock and set up for a next bus transfer in the next clock.

Abstract: A shared interleaved memory having a relatively large number of banks employs circuitry and methodology for resolving bank conflicts without significantly inducing delay into the data path. A first and a second port make data read, data write, and instruction fetch requests to/from the shared interleaved memory by way of asserting a priority signal, an address, and an operand size which are decoded to discern which, if any, memory banks in the interleaved shared memory are needed. In the event of a bank request conflict, the highest priority requester gets all its requested banks and the losing requester gets all nonconflicting requested banks. After the banks in the interleaved memory are allocated, a signal identifying that the losing requester did not receive all its requested banks is generated which does not impact the delay in the data path and accordingly, the losing requester resubmits its request on the next cycle.

Abstract: In a processor having a protected mode of operation in which a computer memory associated with the processor contains global and local descriptor tables addressed by a combination of a base address and an index, the processor having (i) global and local base address registers alternatively to provide the base address and (ii) a selector for containing the index and a table indicator (TI) bit indicating which of the global and local base address registers is to provide the base address, the processor requiring a time to derive the index and a value of the TI bit and a further time to combine the index and the base address, a base address register predicting circuit to predict, and a method of predicting, which of the global and local base address registers is to provide the base address without having to wait for the processor to derive the value of the TI bit.

Abstract: A configurable NAND/NOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The NAND/NOR logic element (FIG. 3, 50) is configurable as either a NAND or a NOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). C inputs control p- and n-channel transistors. Depending on whether the C input is deasserted or asserted, respective internal nodes are shorted to effect the selected configuration. Specifically, deasserting C provides the NAND configuration, while asserting C provides the NOR configuration. In an alternative embodiment, the NAND/NOR logic element can be used in a full adder to provide the carry output.

Abstract: A pre-charge load device to pre-charge an input on a sense amplifier is coupled between a positive voltage rail and the input to the sense amplifier and is biased by a bias network coupled between the positive voltage rail and the sense amplifier input to adapt the sense amplifier slew rate in relation to large or unpredictable capacitive impedance changes on the sense amplifier input.

Abstract: A superscalar superpipelined microprocessor having a write buffer located between the core and cache is disclosed. The write buffer is controlled to store the results of write operations to memory until such time as the cache becomes available, such as when no high-priority reads are to be performed. The write buffer includes multiple entries that are split into two circular buffer sections for facilitating the interaction with the two pipelines of the core; cross-dependency tables are provided for each write buffer entry to ensure that the data is written from the write buffer to memory in program order, considering the possibility of prior data present in the opposite section. Non-cacheable reads from memory are also ordered in program order with the writing of data from the write buffer. Features for handling speculative execution, detecting and handling data dependencies and exceptions, and performing special write functions (misaligned writes and gathered writes) are also disclosed.

Abstract: A combination multiplier/shifter circuit (FIG. 2) can be used to implement an arithmetic or execution unit, using the multiplier/shifter to perform both multiplication operations and shift operations (such as for alignment or normalization). The arithmetic unit includes separate multiplier and adder channels. The multiplication channel includes a Multiplier/Shifter Circuit (10) with both multiplication and shift logic. The multiplication logic comprises an Adder Tree 12 with a rectangular aspect ratio (71.times.12) and Booth Recoder Logic 14, and implements conventional Booth recoded multiplication. The shift logic comprises Shift Control Logic 20 and Shift Extender Logic 32. For multiplication operations, redundant partial/final products MS1 and MS2 (sum and carry) are generated as the multiplication output, with conversion to nonredundant partial products, and the addition of partial products to obtain a final product, being performed in the adder channel.

Abstract: Shift-based control logic is used, in an exemplary embodiment, to implement in a microprocessor a circular prefetch queue that stores variable length instructions and transfers four instruction bytes at a time to an instruction decoder. The prefetch queue (10) includes a 16 byte sequential prefetch buffer (12). Access to the buffer is controlled by the shift-based control logic (14) which includes shifter logic that defines a four byte transfer window corresponding to an index byte together with the next three bytes in sequence. For each four-byte transfer operation, the shifter logic enables the four bytes within the transfer window to be read out for transfer to the instruction decoder (20). A transfer operation is initiated by the decoder, which presents the shift-based control logic with a bytes-used indicator, or shift increment. The shift increment denotes the number of bytes used by the previous four byte transfer via a four bit, one-hot selection.

Abstract: A configurable XNOR/XOR logic element is used, in an exemplary embodiment, in an array of spare gates included in a processor or other integrated circuit. The XNOR/XOR logic element (FIG. 4, 60) is configurable as either an XNOR or an XOR gate by a C (configuration) input (that can be metal configurable as either asserted or deasserted). Inverted and noninverted C inputs control two coupling circuits: (a) coupling circuit C10 includes p-transistors C11, C12, C13, and C14, and (b) coupling circuit C20 includes n-transistors C21, C22, C23, and C24. Depending on whether the C input is deasserted or asserted (and the inverted C input is correspondingly asserted or deasserted), these configuration transistors series or cross couple parallel stacked p- and n-transistors that receive inverted and noninverted A and B inputs to effect the selected configuration. Specifically, deasserting C provides the XOR configuration, while asserting C provides the XNOR configuration.

Abstract: An adjustable duty cycle clock generator is disclosed having a single delay line cascaded to a multiplexer and first and second edge detectors which respectively drive set and reset inputs on a S-R latch to produce an adjustable duty cycle clock signal.

Abstract: A write-back coherency system is used, in an exemplary embodiment, to implement write-back caching in an x86 processor installed in a multi-master computer system that does not support a write-back protocol for maintaining coherency between an internal cache and main memory during DMA operations. The write-back coherency system interrupts the normal bus arbitration operation to allow export of dirty data, and includes an X%DIRTY latency-control function. In response to an arbitration-request (such as HOLD), if the internal cache contains dirty data, the processor is inhibited from providing arbitration-acknowledge (such as HLDA) until the dirty data is exported (the cache is dynamically switched to write-through mode to prevent data in the cache from being made dirty while the bus is arbitrated away).

Abstract: Exponent conversion logic implements floating point exponent conversion of single/double precision to an extended format (IEEE 754 standard), such as in the floating point unit of an x86 processor. The SP (single precision)/DP (double precision) to EP (extended precision exponent conversion technique avoids using an adder (with the attendant propagation delay). For SP exponents (8 bit), the exponent conversion logic implements conversion to EP format (15 bits) as follows (FIG. 3a): (a) transferring the 7 LSB (least significant bits) of the SP exponent (41) as the corresponding 7 LSBs of the EP format (42), (b) inverting the MSB (most significant bit) of the SP exponent and using it as the 7 next most significant bits of the EP format, and (c) transferring the MSB of the SP exponent of the MSB of the EP. The operation for converting DP exponents (11 bits) to EP format is analogous. The same exponent conversion techniques are used to reconvert extended format exponents to single and double precision exponents.

Abstract: A sequencer for use in a pipeline architecture includes circuitry for determining whether the previous instruction was a conditional jump instruction and whether the condition was met, circuitry for determining whether the current instruction is a conditional jump, and circuitry inhibiting a branch responsive to the current instruction, if the previous instruction was a conditional jump and the condition was met. Additionally, circuitry may be provided for treating a CALL instruction as a one-cycle unconditional jump if the preceding instruction was a conditional jump and the condition was not met, thereby implementing a two-cycle IF-THEN-ELSE instruction.

Abstract: A parity circuit generates an output parity bit responsive to a plurality of data input bits. The parity circuit comprises a plurality of transistor stages coupled to the input bits and the output bit, the value of the input bits defining at least one charging path through the transistor stages. The charging path is coupled at first and second nodes to a power supply, such that the charging path is supplied with current at both ends, thereby increasing the responsiveness of the parity circuit.

Abstract: An improved sense amplifier is disclosed employing bleeder and dampening devices coupled in a robust feedback configuration for maintaining a relatively narrow and stable voltage level above the high threshold of the sense amplifier.

Abstract: An exception handling system is used, in an exemplary embodiment, to provide exception handling for prefetched instruction bytes in a pipelined 486-type microprocessor. The microprocessor includes a prefetch unit (22) that controls the loading of a prefetch queue (24), including appending a valid bit to each prefetched instruction byte--this valid bit is conventionally used to notify an instruction decoder (26) that a transferred instruction byte is not valid (such as resulting from a change of flow), causing the decoder to signal a stall condition. According to the exception handling technique of the invention, if the prefetch unit detects that any of a selected number of exception conditions (such as limit violations and page faults) applies to a prefetched instruction byte, it invalidates that instruction byte by clearing the valid bit.

Abstract: A current source suitable for use as a loop filter in a phase-locked loop having two aspects of automatic gain control one for prohibiting the voltage controlled oscillator from stopping as the input voltage approaches the limits of the oscillator and another to compensate for current limiting drain to source voltage drops.