Abstract: I/O lines on a CMOS circuit are precharged to preferred voltage levels in order to avoid latch up. The precharging is achieved by using N channel transistors to provide a precharge which is at a threshold voltage (V.sub.T) below bias voltage V.sub.CC, or (V.sub.CC -V.sub.T). This results in a lower forward bias when V.sub.CC bumps down after the I/O lines are floated. By lowering the precharge voltage by a level corresponding to a threshold voltage (V.sub.T), the allowed range of power supply voltage bumping is increased by this amount. This eliminmates the destructive effect of a negative bump of V.sub.BE, which would have presented a diode forward bias condition. Instead, the power supply may bump to (V.sub.BE +V.sub.T).

Abstract: Apparatus for comparing outputs of two digital devices and counting digital aberrations between them. One embodiment of this invention is the use of an XOR gate to compare the output of a DRAM under test to the output of a known good DRAM of corresponding operating characteristics, and the use of a counter to count the digital aberrations, known as badbits, between the two DRAMs.

Abstract: Valve and channeling improvements in a filter pump head assembly used for dispensing photoresist in a semiconductor manufacturing facility.

Abstract: A pumpdown circuit uses voltage sensing to bring a low node to a potential of V.sub.SS +V.sub.T by first grounding the node and then floating the node to the V.sub.SS +V.sub.T potential. When a sensing node is at the V.sub.SS +V.sub.T potential, the sensing node is maintained at a level above ground by leakage current through a pump-up circuit. Biasing the digit and digit* lines to a potential V.sub.T above ground reduces current (amperage) requirement, because the digit and digit* lines do not have to be discharged completely to ground. The momentary discharge of the sense amp node to ground allows the sense amp to behave like a conventional sense amp during initial sensing, thereby allowing a minimum digit/digit* sensing potential to approximate ground plus V.sub.T.

Abstract: A three port memory device has two serial ports and a random access memory port. The random access memory port is addressed to a random access memory in a conventional manner, using RAS and CAS address signals. Data may also be supplied and retrieved through two serial ports to a pair of serial access memories for transfer between the serial ports and the random access memory. This configuration permits formatted data to be simultaneously assessed through the two serial ports, while the random access memory port is being accessed.

Abstract: An R-F electrode apparatus is provided featuring self-adjusting, spring biased electrodes, removably attached to a removable substrate holder, within a chamber used for plasma reactive treatment processes, particularly those involving semiconductor wafers. The apparatus further features base electrodes shaped and supported to insure uniform transmission of electrical energy during operation. The apparatus also provides an automatic means for wiping, self-cleaning action between the contact surfaces of opposing electrodes during introduction and removal of the substrate holder from the reaction chamber. The base electrodes are removably attached to standard electrical feedthroughs located in the reaction chamber wall, which lead to an external R-F power supply.

Abstract: A printed circuit board is designed to conform to a single in-line memory module (SIMM) configuration, but includes multiple rows of the memory devices. By controlling a sequence of enable signals, selection of a single row from the multiple row of memory devices can be accomplished. The ability to address the different rows multiplies the memory capacity of the board by the number of rows of memory devices.

Abstract: Apparatus to enclose a resistivity probe, to be used with a semiconductor wafer washer. Said apparatus is detachable and easy to maintain; is made of readily available and inexpensive plumbing parts; substantially encloses said probe, reducing contamination; allows nitrogen purge of said probe, keeping it clean; fully submerges said probe in discharge fluid, improving measurement accuracy; and is compact enough to allow washers to be triple stacked.

Abstract: A semiconductor memory device such as a dymanic random access memory (DRAM) is formed by first forming a burried contact in a silicon wafer and patterning a series of transistors. After the transistors are patterned, oxide layers are applied and the transistors are etched. Cell bottom plates are then formed and electrical connections between the transistors and a periphery are established. The establishment of the transistors are to forming the cell bottom plates and its more efficient manufacture of the DRAM devices and increases manufacturing yield.

Abstract: A plasma dry etch chamber is provided with an anode plate which has a cooling jacket which extends radially outwardly from a cooling core to an extent corresponding to the radial dimension of a silicon wafer work product. In order to further reduce deposit formation, the outer perimeter of the anode is designed to reduce the effects of polymer deposition.

Abstract: A CMOS transistor is fasbricated by forming the n-wells with both phosphorus and arsenic implants. The arsenic, with its lower diffusion coefficient, tends to concentrate near the top surface of the n-wells, with the phosphorus penetrating sufficiently to define the n-wells at the desired depth. A boron channel stop implant is later applied without masking over the n-wells. Since the arsenic implant is concentrated near the surface, the arsenic impurities overcome the effects of the boron impurities. Additional boron required for n-channel channel stop is provided by n-channel transistor punch-through implantation.