Abstract: A self-contained, self-configurable cascadable pipelined processor chip (160) is diclosed. The chip contains a computation section (FIGS. 1a-1d) which consists of various types of computation circuits (20-42) that can be software-interconnected in any desired configuration by a set of multiplexers (44-52) whose settings are under the control of a control section (FIG. 2 ). The control section consists of various types of control circuits (60-76) which are also software-interconnectable in any desired configuration under program control. The chip (160) is configured by a very long instruction word and then executes the algorithm defined by that configuration iteratively until stopped. The chip (160) can be programmed to reconfigure itself in response to computation results or other selectable parameters, either in accordance with internally stored configurations or in accordance with configuration information stored in an external random access memory (56, 58).

Abstract: A connectivity algorithm hardware implementation system wherein a subject pixel in a raster-scanned digitized image is declared a pixel of interest, in real time, by it being part of a potential target where every pixel on a closed pixel path enclosing the subject pixel differs in intensity from the intensity of the subject pixel by a predetermined intensity level, the system including a sequential delay line array producing a plurality of sequentially delayed digitized video signals representative of the spatial relationship of the pixels in the digitized image, these signals being coupled to a magnitude comparator array along with a delayed subject pixel contrast signal produced by a threshold circuit coupled to the subject pixel intensity causing the comparator array to produce a plurality of resultant signals representative of a comparison of the video signals with the subject pixel contrast signal, which resultant signals are coupled to a path checking circuit that simultaneously identifies all predeterm

Abstract: In a FLIR target detection system, true targets (52) are isolated from potential false target indications produced by background clutter through the use of a connectivity algorithm which attempts to find around each potential target (52) a closed path (65) of lower (or higher) intensity without exceeding a predetermined distance from the centroid (64) of the potential target. If the attempt is successful, the potential target (52) is a true target; if not, it is clutter.

Abstract: A pre-processor (10) for target trackers is disclosed which allows several image analysis algorithms to be computed simultaneously so as to provide improved real-time target recognition. The pre-processor (10) is also equipped to compensate for the rapid rotation of the target image when the tracking aircraft performs abrupt turning maneuvers.