Abstract: A single-event upset tolerant sense latch circuit for sense amplifiers is disclosed. The single-event upset tolerant sense latch circuit includes a first set of isolation transistors, a second set of isolation transistors, a first set of dual-path inverters, a second set of dual-path inverters, and an isolation transistor. The first set of isolation transistors is coupled to a first bitline, and the second set of isolation transistors is coupled to a second bitline. The second bitline is complementary to the first bitline. The first set of dual-path inverters is coupled to the first set of isolation transistors, and the first set of dual-path inverters includes a first transistor connected to a second transistor in series along with a third transistor connected to a fourth transistor in series.

Abstract: An extended temperature operating range low pressure discharge lamp (10) including: an envelope (12) containing an ionizable medium (20) at a selected pressure; an electrode (16, 18) sealed at each end of the envelope (12) for sustaining an electric discharge through the ionizable medium; and a volume variation control for varying the volume of the ionizable medium (20) in response in variations in temperature within the envelope, wherein the volume variation control includes at least one control volume (of gaseous pressure 40) containing a specified volume of the ionizable medium and an aperture (34) communicating between the envelope (12) and the at least one control volume, wherein the at least one control volume includes a sliding piston (36) for varying the volume of the ionizable medium (20) within the envelope (12).

Abstract: A central control system is described that affords intuitive and easy control of numerous subsystems associated with a police car or other emergency vehicle and reduces the cockpit clutter associated with present control systems. A single user interface device is associated with a central controller capable of receiving input commands and outputting device control commands to a plurality of controlled devices or subsystems. Preferably, the central controller comprises a programmable digital computer. An emergency response system is also described which rapidly coordinates and controls operation of a plurality of emergency subsystems associated with the vehicle in accordance with a predetermined scheme of operation for the devices. In one preferred embodiment, the controller receives a single input command and, in response, provides specific device control commands to several individual controlled devices on a relatively simultaneous basis.

Abstract: A single event upset hardened multiport memory cell to be utilized in a register file is disclosed. The single event upset hardened multiport memory cell includes a storage cell, a write bitline, a read bitline. The storage cell, which is utilized for storing data, includes first and second sets of cross-coupled transistors and first and second sets of isolation transistors. The first and second sets of isolation transistors are respectively coupled to the first and second set of cross-coupled transistors such that two inversion paths are formed between the two sets of cross-coupled transistors and the two sets of isolation transistors. Coupled to the storage cell, the write bitline inputs write data to the storage cell. Also coupled to the storage cell, the read bitline outputs read data from the storage cell.

Abstract: A method for compressing data within a data processing system is disclosed. Each unit of data is at least two bytes. As each byte from a data stream is received, a determination is made as to whether or not an identical data byte occurs at a pre-selected interval within a group of bytes already received. In response to a determination that an identical data byte occurs at a pre-selected interval within a group of bytes already received, only a portion of a subsequent unit of data from the data stream is passed to an output.

Abstract: A mechanism for cache-line replacement within a cache memory having redundant cache lines is disclosed. In accordance with a preferred embodiment of the present invention, the mechanism comprises a token, a multiple of token registers, multiple allocation-indicating circuits, multiple bypass circuits, and a circuit for replacing a cache line within the cache memory in response to a location of the token. Incidentally, the token is utilized to indicate a candidate cache line for cache-line replacement. The token registers are connected in a ring configuration, and each of the token registers is associated with a cache line of the cache memory, including all redundant cache lines. Normally, one of these token registers contains the token. Each token register has an allocation-indicating circuit. An allocation-indicating circuit is utilized to indicate whether or not an allocation procedure is in progress at the cache line with which the allocation-indicating circuit is associated.

Abstract: A method and system of providing a cache-coherency protocol for maintaining cache coherency within a multi-processor data-processing system is disclosed. In accordance with the method and system of the present invention, each processor has a cache hierarchy of at least a first-level cache and a second-level cache, and the first-level cache is upstream of the second-level cache. Each of the caches includes multiple cache lines, each associated to a state-bit field utilized for identifying at least six different states of the cache lines, including a Modified state, an Exclusive state, a Shared state, an Invalid state, a Recently-Read state, and an Upstream-Undefined state. In response to an indication of a cache line containing a copy of information that was most recently accessed, the state of the cache line is transitioned from the Invalid state to the Recently-Read state.

Abstract: A method and system for translating a non-native bytecode to a set of codes native to a processor within a computer system is disclosed. In accordance with the method and system of the present invention, a computer system capable of translating non-native instructions to a set of native instructions is provided that comprises a system memory, a processor, and an instruction set convertor. The system memory is utilized to store non-native instructions and groups of unrelated native instructions. The processor is only capable of processing native instructions. The instruction set convertor, coupled between the system memory and the processor, includes a semantics table and an information table. In response to an instruction fetch from the processor for a non-native instruction in the system memory, the instruction set convertor translates the non-native instruction to a set of native instructions for the processor by accessing both the semantics table and the information table.

Abstract: A network adaptor for receiving and processing Asynchronous Transfer Mode cells within a computer network is disclosed. The network adaptor includes a raw cell buffer, a control table, several Direct Memory Access buffers, and a Direct Memory Access controller. The raw cell buffer is utilized for receiving Asynchronous Transfer Mode cells from the computer network. The control table includes a multiple of virtual circuit identifier entries. When a corresponding virtual circuit identifier of the Asynchronous Transfer Mode cell is found in one of the multiple of virtual circuit identifier entries within the control table, one of the several Direct Memory Access buffers is set to receive the Asynchronous Transfer Mode cell.

Abstract: A method and system for characterizing interconnect data within an integrated circuit in order to facilitate parasitic capacitance estimation is disclosed. An integrated circuit typically includes a substrate layer and several metal layers. In accordance with the method and system of the present invention, an overlapping area of interconnect wires is first identified within the integrated circuit. This overlapping area, which is a polygon, may be formed between the substrate layer and at least one interconnect wire in one of the several metal layers. The overlapping area may also be formed between two interconnect wires, each in a different one of the several metal layers. A netname for the overlapping area is then recorded. Finally, a netname of an interconnect wire in a metal layer that is at the same level of an interconnect wire within the overlapping area and an associated distance from each side of the overlapping area is recorded, for every interconnect wire within the overlapping area.

Abstract: A method and system for providing device driver configurations on demand during runtime within a computer system is disclosed. In accordance with a method of the present invention, a Hardware Namespace is constructed by a Hardware Resource Manager and a Logical Device Namespace is constructed by a Logical Device Manager within the computer system. A determination is made as to whether or not the peripheral device is contained within the Hardware Namespace and whether or not a device driver for the peripheral device is also contained within the Logical Device Namespace, in response to a first attempt to access a peripheral device after system boot-up by an application software. In response to a determination that the peripheral device is not contained within the Hardware Namespace, a user is prompted to install the peripheral device within the computer system.

Abstract: An interleaved cache memory having a single-cycle multi-access capability is disclosed. The interleaved cache memory comprises multiple subarrays of memory cells, an arbitration logic circuit for receiving multiple input addresses to those subarrays, and an address input circuit for applying the multiple input addresses to these subarrays. Each of these subarrays includes an even data section and an odd data section and three content-addressable memories to receive the multiple input addresses for comparison with tags stored in these three content-addressable memories. The first one of the three content-addressable memories is associated with the even data section and the second one of the three content-addressable memories is associated with the odd data section. The arbitration logic circuit is then utilized to select one of the multiple input addresses to proceed if more than one input address attempts to access the same data section of the same subarray.