Abstract: A performance monitor implementing a plurality of counters counts several events to provide an instruction fetch bandwidth analysis, a cycles per instruction (CPI) infinite and finite analysis, an operand fetch bandwidth analysis, an instruction parallelism analysis, and a trailing edge analysis. Such analyses are performed on the performance of a data processing system in order that the designer may develop an improved processor architecture.
Type:
Grant
Filed:
December 17, 1996
Date of Patent:
March 9, 1999
Assignee:
International Business Machines Corporation
Inventors:
Frank Eliot Levine, Roy Stuart Moore, Charles Philip Roth, Edward Hugh Welbon