Abstract: A modified partitioning method for placement of a circuit design into a programmable integrated circuit device having a specific distribution of physical resources along a horizontal or vertical line in the device. The circuit design includes a plurality of circuit elements, for example three-state buffers which feed a common bus, or registers which receive a common clock signal. Such elements should or must be placed along a single horizontal or vertical line. One method includes the step of weighting connecting lines (nets) which join circuit elements to be placed along a common line with different weights for the horizontal and vertical directions. Alternatively, elements to be placed along the line are marked to be kept in line during partitioning. A min-cut algorithm then tends to or is required to avoid separating particular elements from a common line.