Patents Represented by Law Firm Armstrong, Westerman, Hattori, McClelland & Naughton
  • Patent number: 6326254
    Abstract: Wells of n- and p-type are formed in a p-type substrate. Wells of p-type are also formed in the n-type well. Both the p-type wells are formed by the same process at the same time to make MOS transistors have different threshold voltages. MOS transistors having a long gate length and a low threshold voltage are formed in the p-well in the n-well, and MOS transistors having a short gate length and a high threshold voltage are formed in the p-well at the outside of the n-well. Fuses are formed over the p-type wells in the n-type well at a high density.
    Type: Grant
    Filed: May 1, 1998
    Date of Patent: December 4, 2001
    Assignees: Fujitsu Limited, Fujitsu VLSI Limited
    Inventors: Taiji Ema, Satoru Miyoshi, Tatsumi Tsutsui, Masaya Katayama, Masayoshi Asano, Kenichi Kanazawa
  • Patent number: 6005761
    Abstract: An overheat protection device 10 that can perform the immediate resetting of the power cutoff control state or the power limit control state when the overheat state of the drive circuit (power MOSFET) is eliminated. A semiconductor switching apparatus and an intelligent power module 30 are also provided which use the overheat protection device 10. The overheat protection device 10 monitors the energized state of the drive circuit that drives the load 32; when it detects the overheat state of the drive circuit during the energized state, resets the energized state to limit or stop the driving of the load 32; holds the power limit control state or the power cutoff control state and monitors the overheat state in synchronism with the timing signal 102b having a predetermined cycle; and, when the absence of the overheat state is detected during the monitoring, generates the gate control signal 108a to reset the power limit control state or the power cutoff control state.
    Type: Grant
    Filed: April 27, 1998
    Date of Patent: December 21, 1999
    Assignee: Yazaki Corporation
    Inventors: Takaaki Izawa, Tsuyoshi Uchikura
  • Patent number: 5618744
    Abstract: According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.
    Type: Grant
    Filed: September 22, 1993
    Date of Patent: April 8, 1997
    Assignees: Fujitsu Ltd., Fujitsu VLSI Ltd.
    Inventors: Rieko Suzuki, Kiyoshi Saida, Kazushige Itazu, Eiji Fujine, Yoshihiro Kamiya, Yoshitaka Uchida, Takako Murakami, Teruhisa Tsuyuki, Kazunori Kawazoe, Takeshi Shimazaki, Yukimi Nishiwaki
  • Patent number: 5582056
    Abstract: An installation for cutting a knife material which accurately cuts and produces an intermediate knife material to be supplied to a bending device for bending and forming a knife for working a sheet body. The installation is provided with a repository member horizontally stocking different kinds of assorted and piled knife materials, a conveyance conveying the knife materials at the repository member to a predetermined spot one by one from the uppermost material, a receiving mechanism horizontally receiving the knife material dropped from the conveyance, an inductive guidance mechanism adjusting the knife material to a proper position and guiding the longitudinal traveling of the knife material, a feeding mechanism feeding the knife material to the longitudinal direction, and a cutter cutting the knife material fed by the feeding mechanism to a predetermined length and produce an intermediate knife material.
    Type: Grant
    Filed: November 14, 1994
    Date of Patent: December 10, 1996
    Assignee: Itami Industrial Co., Ltd.
    Inventor: Chuji Yanagimoto