Patents Represented by Attorney, Agent or Law Firm Arthur I. Navarro
  • Patent number: 6339254
    Abstract: A stacked multichip assemblage including a plurality of integrated circuit die directly attached to a substrate having pads corresponding to terminals on the die, and interconnections between the die, and also to external contacts. The stacked integrated circuit arrangement includes a first chip(s) having an array of bumped terminals positioned on the corresponding pads of the substrate, a larger integrated circuit chip having perimeter bump terminals located over the first chip, and the terminals directly bonded to corresponding pads on the substrate.
    Type: Grant
    Filed: August 31, 1999
    Date of Patent: January 15, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Vaiyapuri Venkateshwaran, Ji Cheng Yang
  • Patent number: 6338973
    Abstract: A mass production process for semiconductor circuits and modules using a combination of thin film platinum metallization dielectric masking, and three-dimensional laser ablation, in conjunction with a solder combinations and melting temperatures. These combinations have been employed for the fabrication of silicon chips as well as connective substrates. Furthermore, spacing films with adhesive properties on both surfaces have been successfully used for assembling multi-chip cubes.
    Type: Grant
    Filed: August 18, 1997
    Date of Patent: January 15, 2002
    Assignee: Texas Instruments Incorporated
    Inventor: Robert E. Terrill
  • Patent number: 6337445
    Abstract: A bump connection structure and a method of attachment to integrated circuits or packages is provided which comprises a prefabricated core structure coated with solderable metal layers to form a composite bump. Said composite bump is aligned to contact pads of the chip or package which have been coated with solder paste, and the assembly heated to form a metallurgical bond. The prefabricated core structures are comprised of metal, plastic or ceramic of the size and dictated by package standards. The connection structure is preferably lead free.
    Type: Grant
    Filed: March 12, 1999
    Date of Patent: January 8, 2002
    Assignee: Texas Instruments Incorporated
    Inventors: Donald C. Abbott, Douglas W. Romm
  • Patent number: 6331737
    Abstract: A method of encapsulating a semiconductor device comprising the steps of providing a mold having top and bottom halves each with cavities for holding semiconductor devices, and further having gates and runners for feeding encapsulation material into said cavities; lining said cavities with protective plastic films; providing a plurality of semiconductor integrated circuit chips, each having an outline; providing an electrically insulating interposer; assembling said chip and said interposer, loading said assembly into said mold and introducing into said mold a low-viscosity, high adhesion encapsulation material; at least partially curing said encapsulation material, thereby forming a flat, high-luster surface; opening said mold and removing said interposer together with said encapsulated chips from said mold; attaching an array of solder balls to the exposed surface of said interposer; and singulating said encapsulated semiconductor devices, thereby forming devices having an outline substantially the same as
    Type: Grant
    Filed: August 25, 1999
    Date of Patent: December 18, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Tiang Hock Lim, Liang Chee Tay
  • Patent number: 6324406
    Abstract: A method for collecting radio signal timing values for use in determining the location of a mobile station in a wireless network. The method includes acquiring a radio signal timing value from the mobile station's serving base transceiver station. A first handover of the mobile station is initiated from the serving base transceiver station to a second base transceiver station. A radio signal timing value is determined as part of the handover procedure. After the first handover is completed, a second handover of the mobile station is initiated from the second base transceiver station to a third base transceiver station, wherein a third timing value is determined as part of the handover procedure. The second handover is also completed.
    Type: Grant
    Filed: April 27, 1998
    Date of Patent: November 27, 2001
    Assignee: Ericsson Inc.
    Inventor: Bagher Rouhollah Zadeh
  • Patent number: 6320255
    Abstract: The invention relates to a flexible and cost-effective method for fabricating customized rerouting metallization of the circuit contact pads. Localized depositions of insulating as well as conducting paths are provided with the capability for manufacturing multi-layered networks of interconnection. In a gas-filled chamber, either a focused laser, or an unfocussed lased impinging through a mask, is used to locally heat selected areas of the chip surface. The gas decomposes on the heated areas, depositing insulating or conducting material precisely on the heated surface areas, respectively. With this additional flexibility for product design and assembly, a number of interesting new products can now be fabricated which are in demand in both commercial and military markets.
    Type: Grant
    Filed: October 9, 1998
    Date of Patent: November 20, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Robert Earl Terrill, John David Drummond, Gary L. Beene
  • Patent number: 6316822
    Abstract: Multichip semiconductor assembly comprising a semiconductor chip stack comprising first and second chips, each having an active surface including an integrated circuit and a plurality of input/output contact pads, and a passive surface; a leadframe for interconnecting semiconductor integrated circuits having first and second surfaces, a plurality of leads, and a chip mount pad, said leadframe being disposed between said first and second chips, and at least a portion of said passive surface of said first chip being attached to said first surface of said chip mount pad; bonding wire connections between each of said contact pads of said first chip to said first surface of one of said leads, respectively; and solder ball connections between each of said contact pads of said second chip to said second surface of one of said leads, respectively, whereby the connections to at least one of said leads are common between said first and second chips.
    Type: Grant
    Filed: September 15, 1999
    Date of Patent: November 13, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Vaiyapuri Venkateshwaran, Ji Cheng Yang
  • Patent number: 6308477
    Abstract: An isolating plate (10) and insulated bolt assembly (51) for electrically insulating a cabinet (22) for holding telecommunications switching equipment. The isolating plate (10) functions as an installation template to assist an installer with locating and installing cabinets (22) in a telecommunications center. The precut cable ways (12) and mounting holes (14) allow the installer to quickly locate and cut the floor as needed for cables (15) and bolts (26) required to install the cabinet (22).
    Type: Grant
    Filed: June 26, 2000
    Date of Patent: October 30, 2001
    Assignee: Ericsson Inc.
    Inventor: Oscar Santamaria
  • Patent number: 6307458
    Abstract: An inductor configuration (50) comprising a three-legged inductor core (20) with a first leg (22), second leg (24), and third leg (26) integrally extending from a base (28). The first leg (22) and second leg (24) are predisposed and spaced about a first surface (30) of the base (28) to form a first channel area (32). The second leg (24) also forms, along with the third leg (26), a second channel area (34) separated from the first channel area (32) by the second leg (24). The inductor also comprises an inductor winding (36) arranged about the inductor core (20) to provide relatively equal magnetic flux through the first leg (22), second leg (24), and third leg (26) when current flows through the inductor winding (36). The inductor configuration may be used as an input or output inductor for a synchronous rectifier circuit (100).
    Type: Grant
    Filed: September 22, 1999
    Date of Patent: October 23, 2001
    Assignee: Ericsson Inc.
    Inventors: Jun Zhang, Richard Farrington, William Hart
  • Patent number: 6303407
    Abstract: A method for loading solder particles (14) onto an substrate comprising applying a flux (18) directly onto solder particles (14) either prior to or following adhering the solder particles (14) onto adhesive areas (30) of an adhesive coated film (20). The adhesive areas (30) of the adhesive coated film (20) are oriented to correspond with contact pads (42) of a substrate (16). The adhesive coated film (20) is aligned with the substrate (16) to transfer the solder particles (14) to the contact pads (42). The solder particles (14) may then be reflowed to securely attach the solder particles (14) to the contact pads(42).
    Type: Grant
    Filed: January 13, 1999
    Date of Patent: October 16, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Gregory B. Hotchkiss, Gonzalo Amador
  • Patent number: 6303977
    Abstract: A structure and method for forming a hermetically sealed semiconductor chip having an active and a passive surface and four edge sides, each edge side having only a single plane; said active surface having an integrated circuit including multiple deposited layers and a plurality of contact pads, said contact pads having bondable and non-corrodible surface; said deposited layers having exposed portions at said side edges; a protective overcoat impermeable to moisture overlying said integrated circuit; and a continuous sealant layer impermeable to moisture overlying all area of said four side edges, whereby said edge sides are sealed and said chip is rendered hermetic.
    Type: Grant
    Filed: December 2, 1999
    Date of Patent: October 16, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Walter H. Schroen, Judith S. Archer, Robert E. Terrill
  • Patent number: 6294766
    Abstract: A battery cell bypass protection technology for use with NiH2 (or other energy storage) cells on a spacecraft or other high reliability application. The device is a thermally activated switch, designed to bypass the current around a failed (open) or failing cell so that the other cells in the battery are unaffected. One unique aspect of the design is a “pre-loaded” compression action, solder shorting mechanism. Another unique aspect is that the construction employs series redundant heaters and blocking diodes in multi-chip packages. These unique aspects provide consistent and complete shorting to provide a low-resistance cell bypass in any orientation on earth (1g) or in orbit (0g). Another unique aspect is the use of non-lead-based solder that minimizes “creep” over time and temperature.
    Type: Grant
    Filed: July 31, 1999
    Date of Patent: September 25, 2001
    Assignee: Microsemi Corporation
    Inventors: Tracy A. Autry, Fernando C. Lynch, Don Mathes
  • Patent number: 6293520
    Abstract: A cable pulling device for installing a second cable (14) along side an existing first cable (12). The cable puller (10) consists of a body (20) with a motor (22) mounted to the body (20). The motor (22) has an output shaft (24) attached to a drive wheel (26). The drive wheel (26) turns against the first cable (12) to propel the cable puller (10) along the first cable (12). The cable puller (10) also includes a motor controller (28) operably coupled to the motor (22) to control the motion of the motor (22). A cable clamp (30) is attached to the body (20) to secure a second cable (14) as it is pulled into position along side the first cable (12).
    Type: Grant
    Filed: October 12, 2000
    Date of Patent: September 25, 2001
    Assignee: Ericsson Inc.
    Inventor: Russell Wayne Turner
  • Patent number: 6278616
    Abstract: A high density memory module is disclosed comprising a first packaged integrated circuit memory device having therein a first electrically insulating carrier and a first conductive routing pattern integral with said first carrier, and at least a first semiconductor circuit chip; a second packaged integrated circuit memory device electrically connected to said first device, wherein said first and second devices form a module; said second packaged integrated circuit device having therein a second electrically insulating carrier and second conductive routing pattern integral with said second carrier, and at least a second semiconductor circuit chip; and said second conductive routing pattern including means for modifying the architectural organization of said module.
    Type: Grant
    Filed: July 7, 1998
    Date of Patent: August 21, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Tito Gelsomini, Chee Kiang Yew, Yong Khim Swee
  • Patent number: 6271109
    Abstract: A substrate for solder ball assembling a semiconductor device substantially parallel onto said substrate, said device having a plurality of terminals arrayed on a warped surface, comprising an electrically insulating surface including a plurality of discrete metallic areas; said areas having locations matching the locations of said device terminals, and further being suitable for solder ball attachment in surface mount reflow operation; and said areas further having at least one characteristic suitable for accommodating said device warping in solder reflow operation, whereby areas having higher amounts of said characteristic cause said solder balls to become thinner during reflow, resulting in lower solder joint heights, relative to the heights of the remaining solder joints.
    Type: Grant
    Filed: July 21, 2000
    Date of Patent: August 7, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Teddy D. Weygan, Ferdinand B. Arabe, Ronaldo M. Arguelles
  • Patent number: 6268662
    Abstract: A semiconductor assembly comprising a semiconductor chip having an active and a passive surface, said active surface including an integrated circuit and a plurality of bonding pads; said bonding pads having a metallization suitable for wire bonding; an array of interconnects of uniform height, each of said interconnects comprising a wire loop substantially perpendicular to said active surface, each of said loops having both wire ends attached to a bonding pad, respectively, and a major and a minor diameter, said loops being oriented parallel with regard to the plane of the opening and having constant offsets in both direction and magnitude of their apex relative to their bonding pad centers; said wire loops having sufficient elasticity to act as stress-absorbing springs; an electrically insulating substrate having first and second surfaces, a plurality of electrically conductive routing strips integral with said substrate, and a plurality of contact pads disposed on said first surface, with attachment materia
    Type: Grant
    Filed: October 14, 1999
    Date of Patent: July 31, 2001
    Assignee: Texas Instruments Incorporated
    Inventors: Howard R. Test, Wei-Yan Shih, Willmar Subido
  • Patent number: 6266533
    Abstract: A wireless communication network and methodology providing GPS assistance data for positioning of mobiles with built-in GPS receivers (GPS-MS). The system and methodology includes obtaining a site location of the BTS currently serving a GPS-MS to be located, as well as obtaining the air interface time in relation to the absolute GPS time at the BTS currently serving the GPS-MS. Knowing the geographical location of the BTS currently serving the GPS-MS, range measurement assistance data is provided with a time of calculation to the GPS-MS. This information is used by the GPS-MS to obtain GPS measurement data at the indicated time of calculation using this a priori information. The GPS-MS obtains GPS measurement data based on the a priori information quickly, and returns the GPS assistance data to a mobile location center (MLC) which ultimately determines the position of the GPS-MS. The MLC has ephermis data, and converts the air interface time to the absolute GPS time for calculation of the GPS-MS position.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: July 24, 2001
    Assignee: Ericsson Inc.
    Inventors: Bagher R. Zadeh, Shahrokh Amirijoo
  • Patent number: 6265788
    Abstract: A wireless control system (30, 70) for distributing electrical control signals to a plurality of controlled devices (36a, 36b, 36c, 74a and 74b), including an electronic control unit (ECU) (32, 72) adapted to communicate with one or more controlled devices (36a, 36b, 36c, 74a and 74b) and an induction loop (34, 73) coupled to the ECU (32, 72) and adapted to provide a magnetic field within the range of the controlled devices (36a, 36b, 36c, 74a, and 74b). Each controlled device (36a, 36b, 36c, 74a and 74b) includes an induction coil (42a, 42b, 42c, 76a and 76b) tuned to couple signals modulated within the magnetic field of the induction loop (34, 74). The controlled devices (74a and 74b) may include a sensor (82a, 82b) and may be adapted to send a status signal (84) to the ECU (72) via the induction loop (73).
    Type: Grant
    Filed: November 5, 1999
    Date of Patent: July 24, 2001
    Assignee: Ericsson Inc.
    Inventors: Lee Davidson, Eric Valentine
  • Patent number: 6253433
    Abstract: An apparatus and method for efficiently inscribing positioning marks on a ring band, including a positioning plate having a pattern of scribe holes defined therein, wherein the pattern of scribe holes is arranged to permit a jeweler to inscribe positioning marks on a ring band based on a number of desired scribe locations chosen from the pattern of scribe holes. A positioning lever is centered above the positioning plate and includes a positioning needle for placement into a scribe hole chosen from among the pattern of scribe holes, and an angular marker for inscribing positioning marks on a ring band positioned below the positioning lever in a central location of the positioning plate. A ring band mount for maintaining the ring band rigidly in place while the angular marker is utilized to inscribe a positioning mark on the ring band.
    Type: Grant
    Filed: October 6, 1999
    Date of Patent: July 3, 2001
    Inventor: Ronald E. Barron
  • Patent number: 6256214
    Abstract: A self-driven synchronous rectifier circuit having synchronous rectifiers with floating gates for a power converter or signal transformer. The circuit comprises a transformer (49, 70) having a secondary winding with a first and second terminal, a first synchronous rectifier (SQ1) coupled to the first transformer secondary winding first terminal and having a control terminal floating relative to ground and a first drive circuit coupled to the first synchronous rectifier floating control terminal and controlling the first synchronous rectifier. A first control signal is coupled to the first drive circuit, where the first control signal controls the first drive circuit as a function of a polarity reversal of a voltage across the first transformer (49, 70). A second synchronous rectifier (SQ2) is coupled to the first transformer secondary winding second terminal and has a control terminal floating relative to ground.
    Type: Grant
    Filed: March 11, 1999
    Date of Patent: July 3, 2001
    Assignee: Ericsson Inc.
    Inventors: Richard W. Farrington, William Hart