Abstract: An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arrangedas a pipeline processing machine. Control tokens and DATA Tokens pass ovef the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

Abstract: An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

Abstract: A Reed-Solomon decoder includes an optimized Galois Field multiplication circuit. The circuit has a plurality of multipliers, connected in a linear chain, wherein a first multiplicand of the first multiplier is the magnitude A, and the second multiplicand is a constant. The circuit operates on a linear combination of alpha values that sum to .alpha..sup.j, each multiplier in the chain generating a succeeding alpha value. A plurality of selectors enable the outputs of the multipliers according to the magnitude .alpha..sup.j. An addition circuit, preferably realized as a logical network of XOR gates, is connected to the selectors for adding the enabled outputs of the multipliers to form the final product.

Abstract: A positioning system for locating objects in places where standard Global Position System signals do not penetrate. A first embodiment uses a GPS receiver and a clock recovery unit. A computer receives the positional information and accurate time information. The computer calculates new orbital data for at least four pseudosatellites. The pseudosatellites are antennas positioned in an interior or shielded space and function to send pseudosatellite data to a receiver. In a second embodiment, the positions of the pseudosatallites are provided to the computer without the use of a GPS receiver. An accurate clock signal is also provided. The computer calculates orbital data for each pseudosatellite and transmits the time signal and ephemeris data for each pseudosatellite. The time signal is delayed for each pseudosatellite to account for propagation delays due to different connecting cable lengths.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

Abstract: A Huffman Decoder is provided for decoding a data stream of fixed length and variable length codes and is adapted for video decompression applications. In the case of variable length codes, a table index calculation is performed using a ROM whose addresses are controlled by a selector/shifter. This calculation is bypassed in the case of fixed length codes. An index-to-data circuit then yields decoded data.

Abstract: A first embodiment of a cell culture system has a cell death accelerator comprising one or more cell death inducing substances, including serum albumin, hemoglobin, glycine and glutamic acid. In a second embodiment a cell death inhibitor comprises one or more kinds of cell death inhibiting substances which include mercapto group containing amino acids, other mercapto group containing compounds and tryptophan. In a third embodiment a cell death inhibitor comprises an inhibitor of RNA or protein synthesis, optionally augmented with a thiol. The system can be applied to selectively induce death of cultured cells, such as neoplastic cell lines, or to inhibit death of other cells, such as neoplastic cell lines or non-neoplastic cells such as brain cells.

Abstract: A CMOS integrated signal processing system for a sampling receiver includes a timing recovery circuit, wherein an on-chip numerically controlled oscillator is operative at periods T that are initially equal to the nominal baud rate of the signals controls a sinc interpolator receiving samples at the sampling rate. A loop filter is coupled to the sinc interpolator and to the numerically controlled oscillator. The arrangement is capable of handling various symbol rates. The system includes a circuit for carrier recovery, having a second on-chip numerically controlled oscillator, a digital derotation circuit responsive to the second numerically controlled oscillator, accepting an in phase component and a quadrature component of the sampled signals. An adaptive phase error estimation circuit is coupled in a feedback loop.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. The apparatus includes a Huffman decoder for decoding data words encoded according to the Huffman coding provisions of either H.261, JPEG or MPEG standards. Data words in the tokens include an identifier that identifies the Huffman code standard under which the data words were coded. The Huffman decoder responds to the identifier and converts the received data words to JPEG Huffman coded data words. An index number into a lookup table is associated with each JPEG Huffman coded data word, and a decoded data word is generated corresponding to the index number.

Abstract: An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

Abstract: A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Abstract: An integrated CMOS circuit is disclosed for deinterleaving transmitted data packets. The circuit operates with a RAM buffer that is no larger than a block of interleaved data. An optimized addressing scheme is provided that minimizes on-chip hardware. The circuit provides an orderly initialization of the buffer, and a suitable emptying process during a channel change or other interruption of data flow.

Abstract: The invention provides a decoder of symbols of received data, the data being encoded according to a convolutional encoding scheme and transmitted through a communications channel. The data is punctuated according to a puncturing matrix, and has a plurality of state values which describe a sequence of state transitions. The decoder has a generation unit that accepts the received data for calculating metrics of the transitions thereof. A selector responsive to the generation unit selects a path of transitions corresponding to the path produced by a transmitter of the data stream. A traceback unit maintains historical information representative of sequential decision operations of the selector. A counter is provided for counting illegal state transitions of the path selected by the selector, and a control unit, responsive to the counter, determines a puncture rate and adjusts a puncture phase of the received data.

Abstract: An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.

Abstract: The invention provides a RAM interface for connecting a bus to RAM wherein a separate address generator generates the addresses the RAM interface needs to address the RAM. The interface utilizes a plurality of swing buffers, and has a control module for coordinating accesses thereto, which is connected to the address generator by a specialized two-wire interface. The address generator and the source of data are clocked asynchronously and at different clock rates.

Abstract: A CMOS integrated signal processing system for a sampling receiver includes a timing recovery circuit, wherein an on-chip numerically controlled oscillator is operative at periods T that are initially equal to the nominal baud rate of the signals controls a sinc interpolator receiving samples at the sampling rate. A loop filter is coupled to the sinc interpolator and to the numerically controlled oscillator. The arrangement is capable of handling various symbol rates. The system includes a circuit for carrier recovery having a second on-chip numerically controlled oscillator, a digital derotation circuit responsive to the second numerically controlled oscillator, accepting an in phase component and a quadrature component of the sampled signals. An adaptive phase error estimation circuit is coupled in a feedback loop.

Abstract: An integrated digital communication system utilizing multilevel vestigial sideband transmission is provided. The communication system receives a multi-level pulse-amplitude modulated digital signal from a limited bandwidth channel. The system includes processing stages which demodulate, sample and filter the incoming signal prior to recovery of the digital data. Other stages recover the timing and lock on to the frequency and phase of the transmitted signal, as well as provide for automatic gain control. An adaptive equalizer, error correction circuitry, and an output interface recover the digital data and provide for transfer to other devices.

Abstract: An MPEG video decompression method and apparatus utilizing a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system, including memory addressing, transforming data using a common processing block, time synchronization, asynchronous swing buffering, storing of video information, a parallel Huffman decoder, and the like.