Abstract: In accordance with the present invention, an apparatus includes a system bus having memory bank identification signals. Coupled to the system bus are at least two memory modules, each having at least one memory bank, and at least one commander module. The commander module contains decode logic which includes memory mapping registers associated with unique values to be driven on the memory bank identification signals. The memory banks contain compare logic including a virtual node identification register which stores a predetermined value to be compared with the value driven on the memory bank identification signals to determine if the memory bank is the target of the current transaction. Thus, memory banks need not decode the entire system bus address to determine if they are the target of the transaction which reduces the time required to complete a transaction with memory.

Abstract: In a method and system for dynamically improving the performance of a server in a network, a tuning system monitors a workload of the server in real time, monitors a set of internal performance characteristics of the server in real time, and monitors a set of adjustable server parameters of the server in real time. The workload of the server may include the frequency and type of service requests received by the server from clients in the network. The internal server performance characteristics may include, for example, a data cache hit ratio of a data cache in the server. The set of server parameters may include, for example, the overall data cache size or the data cache geometry of the server. The tuning system periodically alters one or more of the set of adjustable server parameters as a function of the workload and internal performance characteristics of the server.

Abstract: A method and apparatus for performing division in accordance with certain bandwidth requirements particular to an implementation is described. A pseudo pipelined approach for performing division using the SRT non-restoring division algorithm is described which uses a minor clock and a major clock cycle time. The number of stages in the division pipeline is a function of the parameters bandwidth requirements of the system. The pseudo pipeline division technique iterates for several minor cycles rather than having individual hardware associated with each minor cycle in the division pipeline. High division bandwidth requirements are provided while minimizing the amount of hardware and the area occupied by the associated hardware.

Abstract: A multiplier in a floating point processor includes a circuit to determine for each bit of the multiplier operand a 3 times booth recode and a booth recode multiplier array which implements a 3 times booth recode multiplication. The multiplier includes logic to determine a fast sign extend to replace bit positions shifted in the array as well as a rounding adder to provide a rounded result while determining the final result from the booth recode multiplier. The multiplier also includes a circuit to determine a contribution to the final multiplication result from a lower order product with out forming the entire product.

Abstract: Apparatus and a related method for managing entities in a complex and, in general, geographically distributed system, such as distributed data processing system. The management approach is defined in terms of a generalized model having management modules integrated into a single cooperative system by a management director kernel. The management modules include presentation modules to provide an interface with users who manage the complex system, access modules to provide an interface with managed entities or devices, and function modules to define various functions that may be performed in controlling or monitoring the managed entities. If the complex system being managed is large, a managed entity and an associated access module may be located on one physical system, while a presentation module is located on another physical system, close to the user, and a function module being used might be located on yet another physical system, for reasons of processing convenience.

Abstract: In a method and system for dynamically improving the performance of a server in a network, a tuning system monitors a workload of the server in real time, monitors a set of internal performance characteristics of the server in real time, and monitors a set of adjustable server parameters of the server in real time. The workload of the server may include the frequency and type of service requests received by the server from clients in the network. The internal server performance characteristics may include, for example, a data cache hit ratio of a data cache in the server. The set of server parameters may include, for example, the overall data cache size or the data cache geometry of the server. The tuning system periodically alters one or more of the set of adjustable server parameters as a function of the workload and internal performance characteristics of the server.

Abstract: The present invention is a method of writing data to a storage system using a redundant array of independent/inexpensive disks ("RAID") organization that eliminates the write hole problem of regenerating undetected corrupt data. The invention also overcomes the need for system overhead to synchronize data writes to logical block numbers that map to the same parity block. A log is constructed and used for storing information relating to requested updates or write operations to the data blocks in the multiple disk array. A separate entry is made in the log for each parity block that must be updated as a result of the write operation. Each log entry contains the addresses of the logical block numbers to which data must be written for that operation. After the new data is written to data blocks in the RAID array, a background scrubber operation sequentially reads the next available entry in the log and performs a parity calculation to determine the parity resulting from the write operation.

Abstract: A digital phase lock loop synchronizes a first signal to a second signal having a predefined frequency. The first signal usually has an instantaneous frequency greater than the predefined frequency, so that the first signal is constantly gaining phase with respect to the second signal. The digital phase lock loop performs periodic correction cycles by detecting a predefined phase relationship between the first signal and the second signal, and when the predefined phase relationship is detected, expanding the first signal in phase by a predetermined amount. Preferably, the first signal is generated by clocking a frequency divider with a clocking frequency, and the first signal is expanded in phase by inhibiting the clocking of the frequency divider for one clocking cycle for each correction cycle. Preferably, the predetermined phase relationship is detected when the second signal has a predetermined logic state coincident with clocking by the clocking signal and a predetermined state of the frequency divider.

Abstract: A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queuing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A floating point processor function is integrated on-chip, with enhanced speed due to a bypass technique; a trial mini-rounding is done on low-order bits of the result, and if correct, the last stage of the floating point processor can be bypassed, saving one cycle of latency.

Abstract: A method for translating a boolean function into a logic circuit using gates from a standard library is provided. The method includes the steps of translating the boolean function into a network comprising a plurality of sub-trees, where each of the sub-trees represents a portion of the function, and where each sub-tree includes a plurality of representations for that portion of the function. The plurality of representations are stored in an alterative logic diagram, which comprises a plurality of ugates. The ugates are data structures which define the inputs and the connectivity of the respective ugate in the sub-tree. The sub-tree is mapped to gates from the standard library by selecting the best sub-tree representation. Accordingly, an improved method of logic synthesis is provided that allows for the optimal representation to be provided by starting with a wider range of inputs to the mapping process.

Abstract: A method of conducting computerized commerce on a number of computer systems connected by a computer network including providing a broker computer system, the broker system having a database of broker scrips, each of the broker scrips representing a form of electronic currency, providing a vendor computer system, the vendor computer system having a database containing products which may be exchanged for the broker scrips, the vendor computer system capable of providing vendor scrips, providing a consumer computer system, the consumer computer system having a user interface wherein a user may initiate transactions in the consumer computer system to obtain one or more of the products contained in the database of the vendor computer system, sending a first request from the user on the consumer computer system to obtain a first broker scrip from the broker computer system, processing the first request in the broker computer system, sending the first broker scrip to the consumer computer system in response to the

Abstract: Information is stored in temporary storage and subsequently transferred to a memory over a bus. The temporary storage is provided with a plurality of entries each of which has a selected size that is smaller than a size of the bus. Information that is designated for a common area of the memory is stored in different entries, and the different entries are linked. Before being transferred to memory, the information from linked entries is assembled. The assembled information is then transferred over the bus to memory. Embodiments of the temporary storage include a write queue and a write buffer.

Abstract: A data processing system includes at least one central processor for executing instructions of software programs. In addition the data processing system includes a memory containing a data structure common to the software programs. The common data structure includes a compressed index data structure. The index structure stores index entries referencing a database. The database includes multiple records, each having a unique address in the database. Each index entry includes a word entry if the index entry represents a compressed encoding of a unique portion of information sequentially parsed from the database. The word entry is followed by one or more location entries which reference occurrences of the portions of information. Each index entry includes a metaword entry if the index entry represents a unique attribute of one or more related words. The metaword entry is followed by one or more location entries referencing occurrences of the attributes.

Abstract: A method and apparatus performs high speed forward or reverse Discrete Cosine Transform (DCT) for video compression and decompression that is optimized in both directions and which uses minimal hardware. This invention can be used to improve the speed of electronic transmission of images, decrease the electronic bandwidth necessary to transmit images electronically, increase the density of electronic storage of images, and speed up image enhancement operations.

Abstract: Automatic shelf-to-shelf address assignment is provided for a plurality of disk drive supporting shelves that are removably contained within a multi--shelf cabinet. Error detection apparatus detects failure in the automatic assignment of shelf addresses. An address input of shelf-N receives a shelf addressing voltage from shelf N+1. Shelf-N checks to ensure that the received shelf-N address voltage is within a correct range. Where-N now increases its shelf-N address by one and applies this incremented address to an address input of shelf-N+1. Accuracy of the shelf-N+1 address input is checked, as are the cable/connectors that connect shelf-N to shelf-N+1. ADC and ADC techniques are used, and operation of the automatic address assignment system is timed.

Abstract: A system and method for rapid panning of graphics images stored as objects in an object records database. The system comprises a computer with memory or memories divided into a several memory regions. The computer is coupled to a monitor for displaying graphics files stored in the database. The memory regions include: a virtual map (VMAP) region including cell maps comprising pointers to linked lists of objects in the database; a backing store region storing a bitmapped image of an entire file, and having the same effective dimensions as the VMAP; a main store region storing a smaller portion of the bitmapped image, the main store region having the same pixel dimensions as a viewing region on the monitor and a movable main store viewing window which permits a view of the subset of the bitmap.

Abstract: A high-performance CPU of the RISC (reduced instruction set) type employs a standardized, fixed instruction size, and permits only simplified memory access data width and addressing modes. The instruction set is limited to register-to-register operations and register load/store operations. Byte manipulation instructions, included to permit use of previously-established data structures, include the facility for doing in-register byte extract, insert and masking, along with non-aligned load and store instructions. The provision of load/locked and store/conditional instructions permits the implementation of atomic byte writes. By providing a conditional move instruction, many short branches can be eliminated altogether. A conditional move instruction tests a register and moves a second register to a third if the condition is met; this function can be substituted for short branches and thus maintain the sequentiality of the instruction stream.

Abstract: A sensing device to detect contaminants of known dielectric value such as hydrocarbons when present in a medium with a different dielectric value such as water comprising a plurality of capacitive members electrically connected to a sensor signal generator including a plurality of sensor channels corresponding to the plurality of capacitive members to generate a sensor signal corresponding to the dielectric value of the medium surrounding each of the plurality of capacitive members and a detect signal generator including a plurality of detect channels corresponding to the plurality of sensor channels to receive the sensor signal of the corresponding sensor channel and to generate a contaminant detection signal when each sensor signal from each sensor channel is within a predetermined range of the dielectric value of the contaminant to be monitored.