Abstract: A reduced area butting contact structure (10') is provided, which is especially suited for four-transistor static RAM cells. A structure is formed which includes a doped silicon region and one or more layers of polysilicon and oxide situated thereabove, one of which layers of polysilicon may be a gate polysilicon. An anisotropic etch is then performed through all upper layers including any upper polysilicon layers which may be present, but stopping at the doped silicon region and any gate polysilicon layers present, to form a contact hole (26'). The contact hole is filled with a conductive plug (32) of a material such as tungsten or polysilicon and etched back. In either case, contact with all polysilicon layers present and the doped silicon region is made. In the anisotropic etching process, a two-step etch is employed.