Abstract: A system and method for carrying out a two-dimensional forward and/or inverse discrete cosine transform is disclosed herein. In one embodiment, the method comprises: (1) receiving multiple data blocks; (2) grouping together one respective element from each of the multiple data blocks to provide full data vectors for single-instruction-multiple-data (SIMD) floating point instructions; and (3) operating on the full data vectors with SIMD instructions to carry out the two dimensional transform on the multiple data blocks. Preferably the two dimensional transform is carried out by performing a linear transform on each row of the grouped elements, and then performing a linear transform on each column of the grouped elements. The method may further include isolating and arranging the two dimensional transform coefficients to form transform coefficient blocks that correspond to the originally received multiple data blocks. The multiple data blocks may consist of exactly two data blocks.

Abstract: A network is described for providing estimates of the current time. The network includes multiple computer systems each configured to provide an estimate of the current time in response to a received request. The computer systems are logically arranged to form a hierarchical structure, wherein the hierarchical structure includes multiple levels ranked with respect to one another. Each of the computer systems is assigned one of multiple levels of trust, and occupies one of the levels of the hierarchical structure dependent upon the assigned level of trust. The level of trust assigned to a given computer system is dependent upon a timekeeping dependability of the given computer system. The assigned level of trust may also be dependent upon a timekeeping security of the given computer system, where the timekeeping security is dependent upon a tamper resistance of the time clock of the given computer system. Methods for delegating a level of trust to a new computer system (i.e.

Abstract: A method of quantizing multiple input values in parallel using SIMD instructions is disclosed. In one embodiment, the method comprises (1) receiving a set of input values Xi; (2) operating on the set of input values to produce a set of binary mask values Ki that are related to the input values Xi by Ki=−1 if Xi>0, and Ki=0 if Xi<0; (3) adding half of a quantization step Q to the input values Xi to obtain sum values; (4) subtracting half of a quantization step Q to the input values Xi to obtain difference values; (5) using the binary mask values to screen out sum values calculated from negative input values; (6) using a complementary binary mask to screen out difference values calculated from positive input values; and (7) combining the screened sum and difference values to determine prequantization values Yi that can be expressed Yi=Xi+Q/2 if Xi>0, and Yi=Xi−Q/2 if Xi≦0.

Abstract: A system and method for switching between input clock signals from different clock sources without losing lock by providing a supplemental correction signal to the loop filter in a phase locked loop (PLL) circuit. The phase detector includes a supplemental correction pulse generator configured to offset, at least partially, the effects of losing an input clock signal from a first clock source failure. The phase detector is coupled to receive the input clock signal and a feedback signal. The phase detector outputs a phase error signal indicative of a comparison between the input clock signal and the feedback signal. The loop filter is coupled to receive the phase error signal and to output an error correction signal. A voltage controlled oscillator is coupled to receive the error correction signal and to generate the output signal of the PLL, with the feedback signal indicative of the output signal. Switching logic is coupled to monitor the input clock signal from the first clock source for a failure.

Abstract: An apparatus and method for generating a cyclic redundancy code with multiple cyclic redundancy code circuits are disclosed. High throughput data protocols can work more robustly if accompanied by high throughput error checking to verify the integrity of the communicated data. One approach of improving the performance of cyclic redundancy code generation hardware that can save money and development time is to combine multiple cyclic redundancy code circuits to perform the error checking. Data received is processed across the multiple cyclic redundancy code circuits. Future cyclic redundancy code circuits can also be combined according to this approach.

Abstract: A tagging and arbitration mechanism in an input/output node of a computer system. A mechanism for tagging commands in an input/output node of a computer system includes a tag circuit configured to receive a plurality of control commands. The tag circuit may also be configured to generate a tag value for each of the control commands. The tagging mechanism may also include a buffer circuit which is coupled to the tag circuit. The buffer circuit may include a plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels for storing selected control commands that belong to the respective virtual channel. Further the tagging mechanism may include an arbitration circuit that is coupled to the buffer circuit and is configured to arbitrate between the plurality of buffers depending upon the tag value for each of the control commands.

Abstract: An apparatus for testing an integrated circuit chip includes a printed circuit device having connector pads, contacts, and traces extending between at least some of the connector pads and the contacts. The printed circuit device has openings therethrough, intersecting the contacts, that are adapted to receive the pins extending from the integrated circuit chip so that the contacts may electrically contact the pins extending from the integrated circuit chip. The apparatus further includes a connector electrically interconnected with at least some of the connector pads. The apparatus is adapted to be disposed between the integrated circuit chip and a chip socket, such that the pins extending from the integrated circuit chip may be inserted through the printed circuit device and into the chip socket.

Abstract: A method for achieving a desired value of electrical impedance between conductors of an electrical power distribution structure by electrically coupling multiple bypass capacitors and corresponding electrical resistance elements in series between the conductors. The resistance elements may be annular resistors, and may provide the designer a greater degree of control of the system ESR. The annular resistors may comprise a first terminal, an annular resistor, and a second terminal. The second terminal may be located within the confines of the annular resistor. The annular resistors may be printed onto a conductive plane (e.g. a power plane or a ground plane), or may be a discrete component.

Abstract: A method for controlling operation of a bus and components coupled thereto is provided. The method is comprised of receiving a request for a bus transaction from one of the components coupled to the bus. Thereafter, the frequency of a clock signal supplied to at least the requesting component is increased, and the requested bus transaction is serviced. The frequency of the clock signal supplied to at least the requesting component is decreased upon completion of the requested bus transaction.

Abstract: A cache controller configured to speculatively invalidate a cache line may respond to an invalidating request or instruction immediately instead of waiting for error checking to complete. In case the error checking determines that the invalidation is erroneous and thus should not be performed, the cache controller protects the speculatively invalidated cache line from modification until error checking is complete. This way, if the invalidation is later found to be erroneous, the speculative invalidation can be reversed. If error checking completes without detecting any errors, the speculative invalidation becomes non-speculative.

Abstract: A multi-bank memory subsystem employing multiple memory modules. A memory subsystem includes a memory controller coupled to a memory bus. The memory bus includes a plurality of data paths each corresponding to a separate grouping of data lines. The memory bus is coupled to a first plurality of memory modules corresponding to a first memory bank. The first memory bank corresponding to a first range of addresses. The memory bus is also coupled to a second plurality of memory modules corresponding to a second memory bank. The second memory bank corresponding to a second range of addresses. A separate memory module of each of the first and the second memory banks is coupled to each data path of the memory bus. Memory modules that are coupled to the same data path are located adjacent to one another without any intervening memory modules coupled to other data paths.

Abstract: A peripheral interface circuit for an I/O node of a computer system. A peripheral interface circuit for an input/output node of a computer system includes a first buffer circuit, a second buffer circuit and a bus interface circuit. The first buffer circuit receives packet commands and may include a first plurality of buffers each corresponding to a respective virtual channel of a plurality of virtual channels. The second buffer circuit is coupled to receive packet commands from the bus interface circuit and may include a second plurality of buffers each corresponding to a respective virtual channel of the plurality of virtual channels. The bus interface circuit may be configured to translate selected packet commands stored in the first buffer circuit into commands suitable for transmission on a peripheral bus.

Abstract: The present invention provides a method and apparatus for updating a directory cache. The method comprises detecting a memory access transaction, determining a retention value based on the type of memory access transaction, and storing the retention value in an entry associated with the memory access transaction.

Abstract: An arbitration mechanism for an input/output node of a computer system. An arbitration mechanism includes a buffer circuit for storing received control commands corresponding to a posted virtual channel and a second virtual channel. Each of the control commands includes an identifier value indicative of the source of the control command. A tag circuit that may generate a tag value for each of the control commands prior to the control commands being stored. The tag value may be indicative of an order of receipt of each of the control commands relative to other control commands and may be dependent upon the identifier value. In addition, an arbitration circuit may arbitrate between control commands stored within the buffer circuit dependent upon the tag value of each of the control commands. The arbitration circuit may select, independently of the tag values, a given control command and having a flag bit set.

Abstract: A thermal protection circuit for high output power supplies. A power supply circuit includes a switching control circuit coupled to a switching regulator circuit. The switching control circuit is configured to generate a plurality of switching control signals for controlling the switching regulator circuit. The power supply circuit also includes a temperature sensitive circuit which includes a thermistor. The temperature sensitive circuit is configured to provide a variable voltage level output to the phase control circuit. The switching control circuit is also configured to suspend operation of the switching regulator circuit upon detecting a predetermined voltage level at the output.

Abstract: A memory module having balanced data input/output contacts. A memory module includes a printed circuit board having an edge connector and a plurality of memory integrated circuits. The edge connector may be adapted for insertion into a socket of a motherboard of a computer system, for example. The edge connector includes a plurality of contact pads on both sides of the printed circuit board. The contact pads are configured to convey data signals, power and ground to and from the printed circuit board. The power and ground contact pads alternate along the edge connector. There are no more than four data signal contact pads without intervening power or ground contact pads.

Abstract: A system for protecting a block in a destination storage device including a data mover operable to move data from a source storage device to the block, and a controller coupled to the data mover, the controller operable to detect an application write request to the block and to stall the application write request while a data move operation initiated by the data mover is terminated.

Abstract: A computer system is presented which implements a system and method for tracking the progress of posted write transactions. In one embodiment, the computer system includes a processing subsystem and an input/output (I/O) subsystem. The processing subsystem includes multiple processing nodes interconnected via coherent communication links. Each processing node may include a processor preferably executing software instructions. The I/O subsystem includes one or more I/O nodes. Each I/O node may embody one or more I/O functions (e.g., modem, sound card, etc.). The multiple processing nodes may include a first processing node and a second processing node, wherein the first processing node includes a host bridge, and wherein a memory is coupled to the second processing node. An I/O node may generate a non-coherent write transaction to store data within the second processing node's memory, wherein the non-coherent write transaction is a posted write transaction.

Abstract: Symmetry in a filter is used to reduce the complexity of an interpolator or a decimator and to simplify derivation of resulting discrete samples. In particular, an inverse relationship between weights applied to two samples is recognized and exploited. An inverse relationship is recognized when a first weight is associated with a first of the samples and a second weight is associated with a second of the samples and a weight which is equivalent to the first weight is associated with the second sample and a weight which is equivalent to the second weight is associated with the first sample. The inverse relationship is exploited by forming two composite weights of the first and second weights and weighting composite sample signals with the composite weights. A first of the composite weights has a value which is one-half of the sum of the values of the first and second weights. A second of the composite weights has a value which is one-half of the difference of the values of the first and second weights.

Abstract: A communications arrangement is described for facilitating transfer of messages among a plurality of processes in a computer system. The communications arrangement comprises a channel data structure, a status daemon and an exit handler. The channel data structure includes a channel status flag normally having one of a plurality of conditions, and a plurality of storage locations each configured to receive message information. The status daemon is configured to determine the operational status of the processes. The exit handler is configured to, in response to the status daemon determining a predetermined condition in connection with at least one of the processes, condition the channel status flag to another of the conditions, thereby to indicate to the other processes a failure condition in connection with the communications arrangement.