Abstract: A system and method for switching between input clock signals from different clock sources without losing lock by providing a supplemental correction signal to the loop filter in a phase locked loop (PLL) circuit. The phase detector includes a supplemental correction pulse generator configured to offset, at least partially, the effects of losing an input clock signal from a first clock source failure. The phase detector is coupled to receive the input clock signal and a feedback signal. The phase detector outputs a phase error signal indicative of a comparison between the input clock signal and the feedback signal. The loop filter is coupled to receive the phase error signal and to output an error correction signal. A voltage controlled oscillator is coupled to receive the error correction signal and to generate the output signal of the PLL, with the feedback signal indicative of the output signal. Switching logic is coupled to monitor the input clock signal from the first clock source for a failure.

Abstract: A remote terminal emulator (RTE) is provided in which substantially all of the time elapsing during an emulated use of a computer system under test is categorized and reported. The time required by the computer system under test to respond to command signals transmitted by the RTE is recorded as a receive time and is measured from completion of the transmission of the command signals to recognition of a pattern specified by the RTE as signifying completion of the response by the computer system under test. As a result the receive time recorded reflects the time required by the computer system under test to (a) process and carry out the command transmitted by the RTE and (b) transmit response data back to the RTE.

Abstract: An apparatus, system, and method for arbitrating for a serial bus in an efficient manner. An arbitration phase includes master devices asserting respective arbitration addresses on the serial bus after initiating communications sequences with a START condition. After the arbitration phase, the controlling master device conveys a data transfer upon the serial bus. The serial bus and the devices connected thereto may operate according to an I2C-compatable protocol. The arbitration address may correspond to a slave address associated with a slave device. Each arbitration address is preferably associated with only one master device. The arbitration address preferably initiates a READ cycle, and the slave device responds with a data byte. The data byte may be stored, discarded, or ignored by the master device, as desired. The arbitration address may not be associated with any slave device coupled to the serial bus.

Abstract: A cluster implements a virtual disk system that provides each node of the cluster access to each storage device of the cluster. The virtual disk system provides high availability such that a storage device may be accessed and data access requests are reliably completed even in the presence of a failure. To ensure consistent mapping and file permission data among the nodes, data are stored in a highly available cluster database. Because the cluster database provides consistent data to the nodes even in the presence of a failure, each node will have consistent mapping and file permission data. A cluster transport interface is provided that establishes links between the nodes and manages the links. Messages received by the cluster transports interface are conveyed to the destination node via one or more links. The configuration of a cluster may be modified during operation.

Abstract: A system and method for memory incoherent verification of functionality of an HDL (Hardware Description Language) design of a computer system component is disclosed. A simulated model of the HDL design receives a memory read stimulus from a stimulus file through a simulated first bus. The simulated model of the HDL design is configured to send its response to the stimulus onto a simulated second bus. A transaction checker receives the response from the simulated second bus and analyzes it to verify operation of the HDL design of the computer system component. The stimulus file and the transaction checker are both stored in the computer system memory. The simulated model's response to the memory read stimulus is evaluated by the transaction checker independently of any previous memory write stimulus from the stimulus file. There is no need to have a previous memory write operation or a master initialization of the system memory for every memory read operation.

Abstract: A method and system for determining the sequence of execution of instructions in a computer under test using trace data generated upon execution of certain ones of the instructions. In one embodiment, the method comprises locating an initial entry in the trace data and scanning the instructions in program order beginning with an instruction indicated by the initial entry. When a branch instruction is encountered, the trace data is examined to determine the subsequently executed instruction. If the branch is unconditional, a corresponding address entry in the trace data indicates the address of the next instruction. If the branch is conditional, a corresponding bitmap entry in the trace data contains a bit which indicates whether the branch was taken. From this bit and the instructions themselves, the next instruction is determined.

Abstract: A bridge for a multi-processor system provides interfaces to an I/O bus of a first processing set, an I/O bus of a second processing set and a device bus. A bridge control mechanism arbitrates between the first and the second processing sets for access to each others I/O bus and to the device bus in a first, split, mode, and monitors lockstep operation of the first and second processing sets in a second, combined, mode. On detecting a lockstep error in the combined mode, the bridge transfers to an error mode. The bridge control mechanism buffers write accesses in a posted write buffer in the error mode pending resolution of the error.

Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.

Abstract: A method and circuit for determining the position of a leading logical one or a trailing logical one in a first n bit operand is disclosed. The method and circuit generates an n bit operand from the first n bit operand. One bit of the n bit operand represents a first logical value while the remaining bits of the n bit operand represent a second logical value. Thereafter, the method and circuit generates a k bit operand relating to the position of the leading or trailing logical one in the first n bit operand. The k bit operand is generated from the n bit operand.

Abstract: A fault-tolerant computer architecture is described wherein the effect of hardware faults is diminished. The architecture employs a main data bus having a plurality of interface slots for interconnecting conventional computer sub-systems. The number and type of sub-systems may vary considerably, however, a central processor sub-system which encompasses the inventive elements of the invention is always included. The central processor sub-system employs a plurality of central processing modules operating in parallel in a substantially synchronized manner. One of the central processing modules operates as a master central processing module, and is the only module capable of reading data from and writing data to the main data bus. The master central processing module is initially chosen arbitrarily from among the central processing modules.