Abstract: A system and method for performing an indirect directory search is implemented. In the indirect search, entry attributes that reference other objects may selectively be searched. An attribute syntax for a distinguished name (DN) which is a reference is defined. If an attribute value belonging to an attribute corresponding to the reference syntax is in an entry found by the search, the value points to another entry in the directory. The attributes (members) of the entry pointed to are selectively retrieved, depending on parameters in the search request.

Abstract: A database schema for storing application data in a relational database backing store of a directory service. The application data has at least some entries with multiple value attributes. According to the invention, the application data is profiled to determine how it may be optimally stored in the backing store. Preferably, single entries having single value attributes are stored in a merged attribute table, while entries having multiple value attributes are stored in per attribute tables. According to the optimization, a majority of the attributes are single valued and are stored in the merged table, and the per attribute tables thus store a relatively smaller number of exceptions. This database schema enhances processing of conventional directory service queries into the backing store.

Abstract: An apparatus and method by which repeaters are able to temporarily or permanently store data in a local repository called a depot. Two uses for the depots are checkpoint restart functionality and the ability to store commonly installed software distributions on nodes closer to their destinations. Large software programs such as Office 95™ can be stored on local repeaters for fast and efficient distribution. A particular distribution can be stored in more than one depot. Depots will provide an interface to allow administrators to list the contents of a depot, store new distributions and delete old distributions. Data may be added to a depot by either an explicit administrator command or by retaining data sent as part of a distribution. Applications can decide what data is appropriate for depoting, and mark those distribution segments as “storable”.

Abstract: A phase detector for use in conjunction with a delay locked loop is provided. Programmable delay elements insert an adjustable delay in a received data stream. The programmable delays stress the setup and hold times of the incoming data. Phase detector sampling logic detects the phase difference between a nominal center of the data window, and the limits on the setup (early) edge of the data value window, and the hold time limit (late time) edge of the data valid window (“guardbands”). A data signal arriving earlier than an early guardband or later than a late guardband may not be correctly sampled, and a guardband failure may be said to have occurred. A state machine detects such guardband errors and provides corrective feedback signals.

Abstract: A system and method for recovering a global history vector is implemented. In deeply pipelined central processing unit (CPU) architecture instruction fetches may precede execution by several processor cycles. A global history vector (GHV) may be used in predicting the branches in a current fetch cycle. Fetch redirection events, such as a cache miss, or a branch misprediction may lead to loss of synchronization of instruction fetches and the GHV. To recover the GHV following a redirection event, registers are provided to hold a GHV being used to predict branches in a current fetch cycle and two subsequent GHVs. On the occurrence of a redirection event, a fetch redirection is generated. GHV update logic detects the fetch redirection and resets the current GHV to a selected one of the stored values.

Abstract: A bus arbiter for a computer system having a bus for connection to a plurality of bus devices where each bus device requests control of bus by use of a bus request signal. The bus arbiter contains logic which incorporates a fairness scheme for controlling and prioritizing the bus request signals based on a predetermined priority of each bus device and each bus device's prior access within a fairness cycle. Each device's prior access is tracked by bits in a data register and is determined by whether or not the device actually received or sent information over the bus, and not by a simple granting of access which could result in a retry signal.

Abstract: A data processing system and method for managing the storage of compiled instructions used in interpretive programming language applications is implemented. As the applications are implemented in an interpreted programming language, the instructions are compiled into byte-codes to be used by a virtual machine and are subsequently stored in a memory. The data processing system and method recognize that a same application may be used repeatedly and periodically. Thus, the data processing system and method diminish the time required to compile the instructions of an interpretive programming language application, while preserving the compilation of interpretive programming code across sessions accessing the code. Additionally, the data processing system and method diminish the time required to download a Java application and, therefore, allow a user to more efficiently access Internet operations.

Abstract: A multiprocessor digital amplifier system is disclosed. A first processor is configured to decode a digital signal from a digital signal source. A second processor configured to provide control signals to the first processor. An expansion unit for communicating instructions and data between the processors and a memory device has a first port coupled to the first processor and a second port coupled to the second processor. The expansion unit includes a state generator with circuitry for selecting one of the first and second ports for receiving a memory device access grant. The first and second ports may be granted access in accordance with a selected arbitration protocol. A duration of the memory device access grant selectably constitutes one of a preselected number of accesses and a preselected timeslice. An amplifier amplifies the decoded digital signal from the first processor.

Abstract: A method of monitoring data distribution progress in a computer network including a Distribution Manager and an end-user terminal communicating with the Distribution Manager through at least one node in the network. The Distribution Manager generates an identifier associated with the distribution along with a routing to the end-user terminal through the network. The Distribution Manager updates a Distribution State Table, maintaining information describing the progress of the distribution, and a Node State Table, maintaining information describing the status of the node in the network. The distribution data is then sent to the end-user terminal via the selected routing. Data are collected at the node from the end-user terminal describing the status of the end-user terminal and those data are transferred to the Distribution Manager. The Distribution Manager updates the distribution State and Node State Tables with the data received from the Node.

Abstract: A system and process for locking database records are implemented. A lock state is selectively set in response to a locking operation request. The lock state constitutes a class in an object-oriented locking service architecture. A locking operation corresponding to the locking operation request is performed on one or more records. The locking operation is implemented by a method of a lock state class in the object-oriented locking service architecture, the lock state class corresponding to a current lock state.

Abstract: A core stabilization apparatus and method are implemented. An inner barrel having a plurality of ports disposed circumferentially and axially in a wall thereof is provided. A gas manifold is attached to a first subsets of the ports. Gas is delivered to an interior of the inner barrel via the gas manifold and the corresponding ports. Drilling mud remaining in the interior of the inner barrel is expelled through a second subset of ports. After expulsion of the drilling mud, a stabilizing compound is injected into the interior via an injection manifold attached to the second subset of ports. Upon curing of the stabilizing compound, the inner barrel and core sample contained therein may be sectioned or otherwise manipulated.

Abstract: An elastic interface apparatus and method are implemented. The elastic interface includes a plurality of storage units for storing for storing a stream of data values, wherein each storage unit sequentially stores members of respective sets of data values. Each data value is stored for a predetermined number of periods of a local clock. Selection circuitry may be coupled to the storage units to select the respective data value from the data stream for storage in the corresponding storage unit. Data is sequentially output from each storage unit in synchrony with the local clock on a target cycle of the local clock.

Abstract: A domino logic circuit has a beta controllable noise margin and an ability to hold an evaluated state until a received clock signal goes to a low state by adding an additional N-channel field effect transistor (NFET) in series with another N-channel field effect transistor, where both of these devices receive the date input signal. Additionally, a P-channel field effect transistor (PFET) also receives the data input signal into its gate electrode. This P-channel field effect transistor is positioned so that it opposes one of the N-channel field effect transistors. The advantages gained by this additional circuitry may also be implemented within a multiplexer circuit.

Abstract: The mechanism to reduce instruction cache miss penalties by initiating an early cache line prefetch is implemented. The mechanism provides for an early prefetch of a next succeeding cache line before an instruction cache miss is detected during a fetch which causes an instruction cache miss. The prefetch is initiated when it is guaranteed that instructions in the subsequent cache line will be referenced. This occurs when the current instruction is either a non-branch instruction, so instructions will execute sequentially, or if the current instruction is a branch instruction, but the branch forward is sufficiently short. If the current instruction is a branch, but the branch forward is to the next sequential cache line, a prefetch of the next sequential cache line may be performed. In this way, cache miss latencies may be reduced without generating cache pollution due to the prefetch of cache lines which are subsequently unreferenced.

Abstract: An apparatus and method for a dynamic wave-pipelined interface are implemented. Data signals received from a sending circuit delayed via a programmable delay device corresponding to each signal before being latched into the receiving device. The programmable delay in each delay device is set according to an initialization procedure whereby each signal is deskewed to a latest arriving signal. Additionally, a phase of an input/output (I/O) clock controlling the latching of the data signals is adjusted so that a latching transition is substantially centered in a data valid window.

Abstract: A method of prefetching addresses includes the step of accessing a stored instruction using a current address. During the access using the current address, a target address is accessed in a branch target address cache. A stored instruction associated with the target address accessed from the branch target address cache is prefetched and the branch target address is indexed with selected bits from the address accessed from the branch target address cache.

Abstract: Circuits and systems for producing a static switching factor on the output lines of dynamic logic devices. A logic device having a dynamic portion and a static portion is implemented. In this way, an output logic state is maintained so long as the value of the Boolean operation being performed by the device does not change. Additionally, static logic elements may perform the inversions necessary to output both logic senses, mitigating the need to provide for dual-rail dynamic logic implementations. An asymmetric clock, permits a concomitant decrease in the size of the precharge transistors, thus ameliorating the area required by the logic element and, obviating a need for keeper device.

Abstract: A bus interface apparatus and method are implemented. A pair of data streams is generated from the stream of data to be launched onto a data bus. Each stream is staged along a corresponding data path that includes a plurality of storage elements. Each path feeds an input of a multiplexer (MUX). The output of the MUX drives the bus, and the MUX selects a data value for launching onto the bus in response to a signal derived from an internal bus clock. The internal bus clock is also used to generate a bus clock that is output to the bus along with the data. The period of the bus clock may be a preselected multiple of the period of a processor clock. The data is staged along the two data streams in response to clocking signals derived from the processor clock. Each of the clocking signals is qualified by a corresponding hold signal, that, when asserted, holds the clocking signals in a predetermined state.

Abstract: Instruction branching circuitry including a plurality of logical stacks each having a plurality of entries for storing an address to a corresponding instruction in memory. A counter generates a pointer to an entry in an active one of the logical stacks, the counter including incrementation logic incrementing a stored pointer value following a Push operation and decrementation logic decrementing the stored pointer value following a Pop operation to the active one of the logical stacks. Selector circuitry selects the active one of the logical stacks in accordance with the performance of the Push and Pop operations.

Abstract: A graphical user interface is implemented to indicate how much of the systems resources are being consumed during a dictation operation, via speech recognition, of a document and its corresponding persistent results information and when said resources are nearing their capacity. An external user may take steps necessary to reduce the information stored within the memory resources of a data processing system implementing this graphical user interface in an efficient and effective manner, through the use of a “commit” signal.