Abstract: A shape-based layout beautification operation can be performed on an IC layout to correct layout imperfections. A shape is described by edges (and vertices) related according to specified properties. Each shape can be configured to match specific layout imperfection types. Corrective actions can then be associated with the shapes, advantageously enabling efficient formulation and precise application of those corrective actions. Corrective actions can include absolute, adaptive, or replacement-type modifications to the detected layout imperfections. A concurrent processing methodology can be used to minimize processing overhead during layout beautification, and the actions can also be incorporated into a lookup table to further reduce runtime. A layout beautification system can also be connected to a network across which shapes, actions, and IC layout data files can be accessed and retrieved.
Type:
Grant
Filed:
December 13, 2006
Date of Patent:
February 23, 2010
Assignee:
Synopsys, Inc.
Inventors:
James K. Falbo, Vinod K. Malhotra, Pratheep Balasingam, Donald Zulch
Abstract: An analog soft-start circuit for a switching regulator (e.g., a buck converter) including an analog ramp circuit and an open-loop analog voltage clamp circuit. The voltage ramp circuit utilizes a two-stage current divider circuit to generate a very low, stable current signal, and an integrator circuit including a relatively small, integral capacitor to generate the ramp voltage signal in response to the very low current signal. The analog voltage clamp circuit clamps the regulated output signal to the ramp voltage until the ramp voltage signal increases to a predetermined voltage level, thereby causing the regulated output voltage to exhibit the desired soft-start characteristics. The analog clamp circuit includes a current mirror circuit that generates a clamp current that pulls down the error amplifier output stage via a clamping element (e.g., a diode) until the ramp voltage signal reaches a predetermined level.
Abstract: A test system for positioning and measuring the far-field pattern of a laser diode under test (LDUT) using a single objective lens and two relay lenses. Positioning is achieved by passing light from the LDUT through a video microscope formed by the objective lens and a first relay lens, which focuses the light onto an image plane for capture by a first camera. Far-field pattern measurement is performed by reflecting a portion of the focused light through a second relay lens, which collimates the light and directs the unfocused light onto an infinity image plane, where it is captured by a second video camera. Angular orientation is achieved using a laser collimator that reflects beam energy from a datum plane of the LDUT. The reflected beam energy forms a point image at the infinity image plane that is used to determine and/or adjust the angular orientation of the LDUT.
Type:
Grant
Filed:
September 24, 2002
Date of Patent:
July 26, 2005
Assignee:
Infineon Technologies North America Corp.
Abstract: An immersive video system is provided which enables a user to interact with immersive video on a variety of platforms. To accommodate different types of platform components, the resolution of the immersive video may be changed. In one embodiment, a pair of immersive videos, one of the immersive videos having a 360° field of view, are simultaneously played in a standard display software program. In another embodiment, a single immersive video mapping an environment greater than 360° is played in a standard display software program. The display software program can be chosen such that it is supported by a variety of platforms. A view window associated with the standard display software program defines the portion of the immersive video shown to the viewer. A control adjusted by the viewer pans the view window around one of the pair of immersive videos.
Abstract: Efficient methods for lithographically fabricating spring structures onto a substrate containing contact pads or metal vias by forming both the spring metal and release material layers using a single mask. Specifically, a pad of release material is self-aligned to the spring metal finger using a photoresist mask or a plated metal pattern, or using lift-off processing techniques. A release mask is then used to release the spring metal finger while retaining a portion of the release material that secures the anchor portion of the spring metal finger to the substrate. When the release material is electrically conductive (e.g., titanium), this release material portion is positioned directly over the contact pad or metal via, and acts as a conduit to the spring metal finger in the completed spring structure. When the release material is non-conductive, a metal strap is formed to connect the spring metal finger to the contact pad/via.
Type:
Grant
Filed:
July 27, 2001
Date of Patent:
December 9, 2003
Assignee:
Xerox Corporation
Inventors:
David Kirtland Fork, Jackson Ho, Rachel King-ha Lau, JengPing Lu
Abstract: A memory system that includes a dynamic random access memory (DRAM) cell including an access transistor and a capacitor structure fabricated in a semiconductor substrate. The capacitor structure is fabricated by forming a cavity in a shallow trench isolation region, thereby exposing a sidewall region of the substrate below the upper surface of the substrate. A dielectric layer is formed over the upper surface and the sidewall region of the substrate. A polysilicon layer is formed over the dielectric layer and patterned to form a capacitor electrode of the capacitor structure that extends over the upper surface and the sidewall region of the substrate. The capacitor electrode is partially recessed below the upper surface of the substrate. The polysilicon layer is also patterned to form the gate electrode of the access transistor.