Abstract: A varistor having a plurality of spaced electrodes positioned on common surface thereof and a conductive layer positioned on the opposed major surface thereof.

Abstract: An improved process for forming multilayer resist structures for lithographic processing of a substrate having topographical features is provided. The structures are comprised of a resist layer having thereover a layer of poly(vinyl pyrrolidone). When the resist layer is a photoresist, the subject structures may optionally contain an absorptive layer directly overlying the substrate and/or a layer of contrast enhancement material overlying the planarizing layer. The poly(vinyl pyrrolidone) optionally contains from about 0.05 to about 0.1 percent by weight of a suitable surfactant, suitably a nonionic surfactant.

Abstract: A power supply switching circuit is disclosed which provides for automatically switching an electrical circuit load from a main power source to an auxiliary power source, yet maintains the two power sources isolated from each other. The power supply switching circuit is readily integrated with its electrical load to form a monolithic integrated circuit. A pair of MOSFETs provides alternate connections of the load to the respective power sources. The circuit effectively connects the gate and source of the appropriate MOSFET across the available power source and thus assures the maximum turn-on voltage is applied to the MOSFET.

Abstract: A video coupler device capable of providing high effective electrical isolation between an analog video signal source system and a signal receiving system is disclosed. The device includes a high-speed LED and a high-speed, linear, integrated circuit. The integrated circuit includes a photodiode, an input current amplifier and an output transimpedance amplifier. The resultant video coupler exhibits a high degree of linearity and stability at a low cost, while requiring minimal external circuitry to handle standard video signals.

Abstract: A parallel EXCLUSIVE or and EXCLUSIVE NOR gate comprising four tri-inverter circuits in which the input transistors of the tri-inverter circuits are shared.

Abstract: A long chain organic acid, such as stearic acid, is used as a flux to bond aluminum to electro-deposited sheet of aluminum, magnesium, or alloys thereof.

Abstract: Level shifter circuitry, as for an operational amplifier, imposes no current load on the preceding amplifier stage associated with its level shifter function. A common-collector-amplifier first transistor has base and emitter connections to the input and output terminals of the level shifter. A second transistor of similar conductivity type and common-collector forward current gain has its base electrode connected through a first current mirror amplifier to the input terminal of the level shifter and has its emitter electrode connected through a second current mirror amplifier to the output terminal of the level shifter. The first and second current mirror amplifiers have similar current gains. The first current mirror amplifier may also be incorporated in apparatus for supplying constant current loading to the preceding amplifier stage, to this end having a source of constant current connected to its input connection.

Abstract: The memory cell is a five transistor cell formed with complementary symmetry metal oxide (CMOS) semiconductor insulated gate field effect transistors (IGFETs) in the silicon-on-sapphire (SOS) technology with doped polycrystalline interconnects using buried contacts. Diodes are formed where doped polycrystalline silicon lines form buried contacts to underlying silicon epitaxial regions of opposite conductivity type and where silicon epitaxial regions of opposite conductivity type contact one another. The presence of these diodes has been shown by the inventor to not be detrimental to the operation of the memory cell.

Abstract: An improved alumina base ceramic guide article is disclosed having sufficient electrical conductivity to remove the static electricity charge from continuously moving textile and synthetic organic polymer filament and tapes when placed in physical contact with said guide article. Specifically said guide article is formed with a sintered polycrystalline alumina ceramic material having a rounded grain size so as not the mechanically abrade the filament or tape members in physical contact therewith and with said ceramic material comprising in approximate weight percent based on the starting batch formulation at least 94% Al.sub.2 O.sub.3, 1-4.5% TiO.sub.2, 0-4% MnO.sub.2, and 0-3% Fe.sub.2 O.sub.3. In the preferred embodiments, the ceramic material contains sufficient TiO.sub.2, Fe.sub.2 O.sub.3, and MnO.sub.2 content to produce a dark uniform color in the final ceramic article.

Abstract: A low resistance silicon conductor for tunnelling under an intervening metal conductor on a semiconductor device is provided. The low resistance conductor includes two layers of highly doped single crystalline or polycrystalline silicon which are stacked so that one is directly over the other. A pair of metal conductors are arranged, one on each side of the intervening metal conductor. Each of the pair of metal conductors is formed in ohmic contact with a portion of each of the two layers of silicon near one of their adjacent edges, thereby forming a two layer conductive tunnel under the intervening metal conductor.

Abstract: A binary input signal, V.sub.IN, having a minimum high level value, V.sub.INHMIN, is directly applied to the gate electrode of a pull-up transistor whose conduction path is connected between a first power terminal and an output terminal. V.sub.IN is also applied via level shift circuitry to the gate electrode of a pull-down transistor whose conduction path is connected between the output terminal and a second power terminal. V.sub.IN is level shifted in the positive direction by a preselected voltage level whereby the pull-down transistor is turned-on even when its threshold voltage is approximately equal to V.sub.INHMIN.

Abstract: A method of fabricating a semiconductor device having a symmetric and complementary P-well and N-well. The novel method involves the introduction of a first dopant type into a semiconductor substrate directly through those regions of an oxide layer and a nitride layer which do not underlie a first mask layer. The first mask layer is removed and a second mask layer is formed. A complementary dopant type is then introduced into the semiconductor substrate directly through those regions of the oxide layer and nitride layer which do not underlie the second mask layer. The second mask layer is removed and the dopant ions are simultaneously subjected to thermal drive in to thereby form adjacent wells of opposite dopant type in the semiconductor substrate.

Abstract: A varistor having opposed first and second major surfaces. A first electrode is disposed on at least a portion of both the first and second major surfaces, and a second electrode is disposed on at least a portion of both the first and second major surfaces. The first and second electrodes are symmetrically disposed on the varistor body about an axis lying midway between and parallel to the first and second major surfaces.

Abstract: In a data processor system, a method for transferring data to and from a random access memory (RAM) with a serial data interface and having accessible word location includes the steps of generating a timing pulse consisting of contiguous time slots each defined by the Nth count of a counter, generating an initial address signal in the first occurring contiguous time slot of the timing pulse with the initial address signal including a read/write command signal, incrementing the initial address signal at each Nth count of the counter to form data address signal, accessing memory locations in the RAM with the initial address signal followed by said data address signals, supplying data words to or reading data words from the RAM at the word locations accessed by the data address signals in response to each Nth count of the counter and when the data address signal contains a write command or a read command signal, respectively.

Abstract: The collector-to-emitter voltage (V.sub.CE) of a transistor switch and its base drive are designed to have maximum specified values when the transistor switch conducts the highest specified load current. The base drive to the transistor switch is reduced when the load current is reduced, or when the beta of the transistor increases or is greater than a minimum specified value. The base drive to the transistor switch is regulated by sensing the V.sub.CE of the transistor switch and producing a control current which decreases with decreasing V.sub.CE and increases with increasing V.sub.CE. The control current is then used to supply a regulated base current to the transistor switch while maintaining the V.sub.CE of the transistor below, the maximum specified value, for values of load current below the maximum specified level.

Abstract: A method for decreasing the turnoff time in a crystalline semiconductor region within a semiconductor device comprises initially providing a semiconductor region having a predetermined density of pinning centers. The semiconductor region is then irradiated so as to yield crystal damage that is equivalent to or greater than that which would be produced by irradiating with 1 MeV neutrons at a fluence greater than approximately 10.sup.13 cm.sup.-2. The region is then annealed at a temperature of approximately 350.degree. to 450.degree. C. for approximately 15 minutes to one hour so as to yield a density of stable recombination centers correlating with the pinning centers that provides a stable minority carrier lifetime within the semiconductor region.

Abstract: The construction of a semiconductor insulated gate device (IGT) is altered to avoid cell latching problems assisted with "hot spot" sites where an atypically high density reverse current tends to flow. IGT cells adjacent these sites are totally or partially disabled by eliminating emitter regions therein to thereby remove any emitter-base junctions from the paths along which the high density reverse current flows. Also the area of emitter electrode ohmic contact is increased at these "hot spot" sites to effectively divert reverse from neighboring, forward current conducting, active cells and thus reduce the density of reverse flow therethrough to safe levels.

Abstract: A comparator for sensing a small voltage differential at, or close to, the operating voltage rails includes first and second means for producing first and second currents and for producing a third current which is indicative of the difference between the first and second currents. The first current varies as a linear function of first (e.g. V.sub.IN) and second (e.g. V.sub.O) voltages, the amplitude of the first current being proportional to that one of said first and second voltage having the largest amplitude. The second current varies exponentially as a function of the difference between the first and second voltages. Comparator means embodying the invention are particularly useful in circuits where a transistor-switch couples an input voltage (V.sub.IN) to an output terminal and the transistor-switch is to be turned-off when V.sub.IN drops below the voltage (V.sub.O) at the output terminal.

Abstract: A method for making a partially radiation hardened oxide comprises forming a first portion of an oxide layer on a semiconductor body of material at a temperature between about 950.degree. C. and 1400.degree. C., preferably between about 1000.degree. C. and 1200.degree. C. Thereafter a second portion of the oxide layer is formed between the semiconductor body and the first oxide layer at a temperature between about 850.degree. C. and 900.degree. C., preferably at about 875.degree. C.

Abstract: A circuit for limiting the load current through a transistor switch, where the load is connected between the collector of the transistor switch and a first power terminal and a resistive element, whose impedance is much less than that of the load, is connected between the emitter of the transistor switch and a second power terminal. The circuit includes first and second comparator transistors, with the emitter of the first transistor being connected to the emitter of the transistor switch and the emitter of the second transistor being connected to the second power terminal. The same potential is applied to the bases of the first and second comparator transistors whereby the difference between their base-to-emitter voltages is equal to the voltage drop across the resistive element. The collector currents of the first and second transistors are compared and the difference in the currents is used to control the conductivity of the transistor switch.