Abstract: A computer system employs a SEC-DED-S4ED rotational error control code (ECC) wherein all columns of H matrix are linearly independent and have an odd weight, and are arranged to allow detection of 4-bit byte errors. The ECC includes check bits arranged in a specific manner in designated columns of the matrix to permit detection and correction of single bit errors, as well as detection of double, triple and quadruple bit errors. The computer system employing the ECC also includes a data path having a variety of implementations; e.g., a single 72-bit path, two 36-bit paths, or a single 36-bit path.