Abstract: A method of on-chip interconnect design in an integrated circuit (IC) is provided. Fast circuit simulations of each net constituting the IC are performed for noise margin and slew rate analysis. A resistor/capacitor (RC) network for each net is generated from net lengths, and assignments of parasitic cross-coupling capacitances and shunt capacitances derived from three-dimensional field solver evaluations of pre-routing phase estimated wire geometries. If the noise margin and slew rate criteria are not satisfied for the net under simulation, the simulations are iterated, with a new wire geometry selected between iterations, until the criteria are satisfied. Each net is tagged with a wire geometry that satisfies noise margin and slew rate requirements which can then be passed to a routing tool.

Abstract: An apparatus and method for renaming a plurality of storage register files implemented. A rename register in a unified rename buffer provides temporary storage for instruction operands resulting from the execution of the instruction to the operands being written to an architected register in one of storage register files. A rename map associates the rename register with the corresponding storage register, which may be in any of the storage register files. The rename registers may simultaneously store data values of different types. Rename map entries include a tag which operates to identify the register file containing the storage register.