Abstract: In a method for generating a mapping of logical addresses to a layout of an electronic circuit structure first and second relations are established. The first relation is representative of the mapping of signal pairs to the layout and the second relation is representative of the mapping of the logical addresses to the signal pairs. Joining of the first and second relations yields a mapping table which can be used for purposes of circuit testing and design.

Abstract: A first current (Iptat) having a magnitude proportional to absolute temperature is passed through a resistor (R3) and a PN-junction (QA) to produce first and second voltages (Vr+Vbe) having, respectively, positive and negative temperature coefficients which when summed provide a temperature stabilized internal reference voltage (Vbgrl). This internal reference voltage (Vbgrl) powers the current generator for currents (I1, 12)) which pass through a second resistor (R8, R9) and a second PN junction (Q20A, Q20B) to produce third and fourth voltages having respectively, positive and negative temperature coefficients which when summed provide a temperature stabilized external reference voltage (Vbgrl) having improved ripple rejection. There is no feedback from the external reference voltage (Vbgr2, V-out) to the first current (Iptat) generator (42).

Abstract: A means and method for providing platinum or tungsten silicide contacts to source, drain, gate and tub regions of a dielectrically isolated MOSFET is described. A "false" gate is used to provide automatic self-aligned separation of the source-drain contact and the tub contact. An intermetallic forming material is uniformly coated over the doped substrate on which the gate and false gate region have been formed in a spaced-apart fashion. Upon heating the intermetallic forming layer reacts with the substrate and the polysilicon gates to form intermetallic regions. The remaining portion of the intermetallic forming layer is differentially etched away from the dielectric isolation walls and the sidewall oxides on either side of the gate and false gate. Alernatively, selective deposition may be used to avoid deposition on the dielectric regions. The false gate extends laterally across the isolation tub. This procedure separates the device contacts from the tub contact without the use of separate masking layers.

Abstract: Dielectric filled isolation walls for semiconductor devices and integrated circuits of improved characteristics and ease of manufacture are formed by etching trenches in a semiconductor substrate and refilling the trenches with multiple layers of silicon oxy-nitride. Alternative oxygen rich and nitrogen rich oxy-nitride layers are used. For the narrowest trenches two layers suffice. Where trenches of different widths are present the wider trenches receive multiple layer pairs. A cap layer of oxy-nitride is added to insure filling of any trench intersections. The oxy-nitride desirably has a composition Si.sub.x O.sub.y N.sub.z where x, y, and z are in the range of 0.25-0.4, 0.27-0.6, and 0.0-0.35, respectively, for the oxygen rich material and where x, y, and z are in the range 0.35-0.43m 0.0-0.35, and 0.28-0.6, respectively, for the nitrogen rich material, expressed in atomic fraction and x+y+z=1.