Abstract: The present invention comprises a method and apparatus for built-in self-test of logic circuitry for logic under test. The logic under test comprises a plurality of test points, each test point having a plurality of nodes. The test circuitry comprises a linear finite state machine. The linear finite state machine generates subsequent states that are non-sequential, pseudorandom binary numbers stochastically determined by a characteristic polynomial of the linear finite state machine. Moreover, the contents of the linear finite state machine are readable or writable via scan. The preferred implementation also comprises a test data bus coupled between the logic under test and the linear finite state machine. The test data bus is configured to convey data in parallel fashion between the linear finite state machine and the selected test point of the plurality of test points.

Abstract: An apparatus that takes two N-nary operands and selectably performs either addition or subtraction on them to produce an arithmetic result and a carry indicator. Carry-lookahead logic is utilized to create HPG signals for each N-nary dit of the intermediate sum of the two operands and also to create “block” HPG indicators for blocks of dits. In the preferred 1-of-4 embodiment, subtraction may be implemented as four's complement addition. The value of each dit of the intermediate sum is incremented by one before final output if a carry has propagated into the dit.

Abstract: The present invention is a method and apparatus that synchronizes logic in an integrated circuit (IC). The present invention discloses a global clock signal with a global phase and an approximately 50% duty cycle. Additionally, the present invention discloses a first local clock signal with a first phase and an approximately 50% duty cycle that couples to a first dynamic logic gate where the first local clock signal is generated from the global clock signal. One or more intermediate local clock signals with one or more intermediate phases are generated from the global clock signal where each intermediate local clock signal has an approximately 50% duty cycle that couples to one or more intermediate dynamic logic gates. An end local clock signal with an end phase and an approximately 50% dutycycle that is also generated from the global clock signal and that couples to an end dynamic logic gate.

Abstract: The present invention discloses a method and apparatus that uses extensions to the TLB entry to dynamically identify pages of memory that can be weakly ordered or must be strongly ordered and enforces the appropriate memory model on those pages of memory. Such identification and memory model enforcement allows for more efficient execution of memory instructions in a hierarchical memory design in cases where memory instructions can be executed out of order. From the page table, the memory manager constructs TLB entries that associate page frame numbers of memory operands with page-granular client usage data and a memory order tag. The memory order tag identifies the memory model that is currently being enforced for the associated page of memory. The memory manager updates the memory order tag of the TLB entry in accordance with changes in the client usage information. In the preferred embodiment, the TLB structure is a global TLB shared by all processors.

Abstract: The present invention is a method and apparatus for an N-NARY logic circuit that uses N-NARY signals. The present invention includes a shared logic tree circuit that evaluates one or more N-NARY input signals and produces an N-NARY output signal. The present invention additionally includes a first N-NARY input signal coupled to the shared logic tree circuit and a second N-NARY input signal coupled to the shared logic tree circuit. The shared logic circuit evaluates the first second and second N-NARY input signal and produces an N-NARY output signal coupled, which additionally couples to the shared logic tree circuit. The present invention uses signals that include 1 of 2 N-NARY signals, 1 of 3 N-NARY signals, 1 of 4 N-NARY signals, 1 of 8 N-NARY signals, and the general 1 of N N-NARY signals. The present invention evaluates any given function that includes the AND/NAND, OR/NOR, or XOR/Equivalence functions.

Abstract: The present invention discloses an apparatus and method for performing carry propagate logic on two 1-of-4 two-bit addends to produce a 1-of-3 carry propagate indicator. The preferred embodiment of the present invention will set an H indicator for a given dit n if the sum of An and Bn is less than or equal to two, will set a P indicator if the sum is three, and will set a G indicator if the sum is greater than three.

Abstract: The present invention uses N-nary logic to perform addition or subtraction, along with carry propagate logic, within one gate. The gate produces as outputs a 1-of-4 result value and a 1-of-3 HPG indicator. The preferred embodiment of the present invention implements subtraction using three's complement addition. In an alternative embodiment, four's complement addition is implemented to achieve the subtract function and the HPG indicator is a 1-of-2 signal that combines the H(alt) and P(rop) indications.

Abstract: The present invention utilizes N-nary logic to implement an add function and a carry-lookahead function within the same gate, producing an N-nary sum and an N-nary HPG indicator.

Abstract: The present invention discloses a method and apparatus for adding two 1-of-N addends to produce a 1-of-N sum. In the preferred embodiment, the addends and sum comprise 1-of-4 logic signals.

Abstract: The present invention is a magnitude comparator that receives as inputs two 32-bit 1-of-4 operands. The magnitude comparator generates a carry indicator if the value of the first operand is less than or equal to the value of the second operand. The magnitude comparator generates a no carry indicator if the value of the first operand is greater than the value of the second operand.

Abstract: The present invention describes a method and apparatus that performs parallel normalization and rounding on an ANSI/IEEE 754-1985 floating point intermediate result that dispenses with the need for shifting of the intermediate result prior to normalization or rounding. The exponent is pre-incremented prior to normalization. During normalization, the most significant bit of the intermediate fraction is shifted into the carry bit and the exponent is decremented accordingly. Selection logic then selects one of six possible formatting procedures to generate a mathematically correct output fraction in proper ANSI/IEEE 754-1985 floating point format, and formatting logic generates the output fraction according to the selected formatting procedure.

Abstract: A memory device having a sense trigger coupled to receive an address when available, and to assert a sense trigger signal to the sense trigger when the sense trigger receives the address. The memory device also has an N-NARY, or 1-of-N, input logic gate that provides additional assurance that no more than one word line is asserted when an address is decoded. The memory device also has an N-NARY, or 1-of-N, output driver logic gate that provides an output signal directly useful for providing to another (N-NARY) 1-of-N logic gate.

Abstract: The present invention describes an apparatus and method that normalizes an ANSI/IEEE 754-1985 floating point arithmetic intermediate result having a fraction and exponent. The exponent is pre-incremented by one prior to normalization. During normalizaion, the most significant binary “1” of the fraction is shifted left until it resides in the carry bit. For each left shift performed, the incremented exponent is decremented once.

Abstract: The present invention describes an apparatus and method to select the format of the output fraction result of an ANSI/IEEE 754-1985 floating point arithmetic operation where parallel normalization and rounding of the intermediate fraction result has occurred. The C bit and the L bit and the most significant bit of the intermediate fraction are examined, along with the Gin bit, Rin bit, and round control bit. Based on these inputs, the output fraction is formatted by performing zero or more manipulations of either the output of the rounder circuit or the output from the normalizer circuit.

Abstract: The present invention is an N-nary equality comparator that receives as inputs two 32-bit 1-of-4 operands. The equality comparator generates an "equal" indicator if the values of the two operands are equal. The equality comparator generates a "not equal" indicator if the values of the two operands are not equal.

Abstract: The present invention describes an apparatus and method that formats the output fraction result of an ANSI/IEEE 754-1985 floating point arithmetic operation where parallel normalization and rounding of the intermediate fraction result has occurred. The output fraction is formatted using all or some of the bits from the output of either the rounder circuit or the normalizer circuit.

Abstract: The present invention comprises a logic device with improved capacitance isolation and a design methodology for reducing unwanted parasitic capacitance in logic circuits. The logic device further comprises an output signal having a first internal evaluate node and a second evaluate node. Additionally, the logic device comprises a first input signal that has a first input wire and a second input wire where the first input wire corresponds to a first possible value of the first input signal and the second input wire corresponds to a second possible value of the first input signal. The logic device further comprises a first plurality of intermediate nodes that includes a first intermediate node. Additionally, the logic device includes a first plurality of transistors that further includes a first transistor coupling the first internal evaluate node to the first intermediate node and being gated by the first wire of the first input signal.

Abstract: A memory device having a sense trigger coupled to receive an address when available, and to assert a sense trigger signal to the sense trigger when the sense trigger receives the address. The memory device also has an N-nary, or 1-of-N, input logic gate that provides additional assurance that no more than one word line is asserted when an address is decoded. The memory device also has an N-nary, or 1-of-N, output driver logic gate that provides an output signal directly useful for providing to another (N-nary) 1-of-N logic gate.

Abstract: The present invention comprises a plurality of clock signals with an approximately 50% duty cycle and overlapping phases. The phases of the plurality of clocks are such that the phase of an individual clock signal overlaps the phase of an earlier clock signal by an amount equal to the overlap of the phase of the next clock signal. The present invention further comprises a plurality of clocked precharge (CP) logic gates coupled in series. An individual CP logic gate couples to an individual clock signal though the CP logic gate's evaluate device. For the data flow through the individual CP logic gate, the logic gate receives its data input from an earlier CP logic gate in the series and passes to the next CP logic gate in the series. The earlier CP logic gate couples to an earlier phase clock signal, and the next CP logic gate couples to the next phase clock signal.

Abstract: A unique combination of software and hardware provides any computer with a system for high speed digital data communications using the computer's standard parallel printer port. The disclosed embodiment of the invention allows any computer with a standard parallel printer port to play or record digital audio sound allowing the computer to serve as a platform for multimedia presentations.