Abstract: The invention provides a method of manufacturing a large-area electronic device, for example a flat panel display, comprising thin-film circuit elements, and also laser apparatus for crystallizing a portion of a semiconductor thin-film (1) with a beam (11) of set energy. The energy of the beam (11) is set in accordance with the output from a light detector (22) to regulate the crystallization of a device portion (3,4 and/or 5) of a semiconductor thin film (1) at which the beam (11) is subsequently directed with its set energy. The light detector (22) monitors the surface quality of a previously crystallized portion (2). In accordance with the present invention, the light detector (22) is located at a position outside the specular reflection path (25) of the light returned by the surface area of the crystallized portion (2) and detects a threshold increase (D) in intensity (I.sub.s) of the light (26) being scattered by the surface area of the crystallized portion.

Abstract: Output stage with self calibrating slew rate control. An output stage comprising a first (1) and a second (2) supply terminal for receiving a supply voltage (SV); a pre-drive circuit (PDS) coupled to an input terminal (IP) for receiving an input signal (V.sub.i), the pre-drive circuit (PDS) comprising a series transistor (TS) with a control electrode (TS.sub.g) for receiving a control voltage (V.sub.cntrl) for controlling a maximum current from an output (PDS.sub.OUT) of the pre-drive circuit (PDS), and a capacitor (C) for retaining the control voltage (V.sub.cntrl); an output-drive circuit (ODS) for delivering an output signal (V.sub.o) at an output terminal (OP) in response to the input signal (V.sub.i); and a control circuit (CC) for delivering the control voltage (V.sub.cntrl). The output stage further comprises a control circuit (CC) which is coupled between the output terminal (OP) and the control electrode (TS.sub.g).

Abstract: A very thin gate oxide is preferably used in non-volatile memories with floating gates for limiting the programming voltage. The minimum thickness of the gate oxide, however, is bound to certain limits in conventional memories because, if the oxide thickness is too small, the loss of charge from a programmed cell would become too great. The gate oxide is thicker than 7 nm in conventional memories for this reason. A non-volatile memory cell according to the invention comprises a gate oxide 9 with a thickness of no more than approximately 6 nm in combination with a p-type floating gate electrode 8. A lower programming voltage can be used thanks to the thin gate oxide, while a good data retention is maintained. The loss of charge is low because the electrons applied to the floating gate during programming recombine there with holes and are bound to the ionized acceptor atoms at a comparatively great distance from the interface between gate and oxide.

Abstract: The invention, relates to a method for enabling a user to input messages into a data prossing system. To each message a respective target zone (202) in a virtual workspace (200) is allocated. A tactual representation of the virtual workspace is generated by applying forces to a member of an input device which has a housing with respect to which the member is user-manipulatable. Manipulations of the member are converted to locations of a control object in the virtual workspace (200). On the basis of the tactual representation the user can navigate through the virtual workspace. A message is selected for input in response to a movement of the control object to a corresponding one of the respective target zones (202). The target zones (202) are arranged in the virtual workspace (200) around a central zero zone (204) being a preferred zone of the control object, such that the target zones (202) have substantially no tangential overlap among one another with respect to the zero zone (204).

Abstract: A circuit for generating a speed value corresponding to a rotational frequency of a rotating shaft. A digital tachometer circuit has a tachometer circuit and a copy/hold circuit. The tachometer circuit maintains an intermediate speed value which is incremented by a gain constant as the rotational frequency increases and is decremented as the rotational frequency decreases. The copy/hold circuit samples the intermediate speed value at selected intervals, thus generating the speed value. The speed value is displayed to a user and represents the vehicle's speed.

Abstract: An output stage comprising an input terminal (IP) for receiving an input signal (V.sub.i); an output terminal (OP) for delivering an output signal (V.sub.o) in response to the input signal (V.sub.i); a first (1) and second (2) supply terminal for receiving a supply voltage (SV); a field effect transistor (Q1) comprising a gate (GN), and a main current path between a source and a drain coupled between the first supply terminal (1) and the output terminal (OP); and slewing control means (SCM) for reducing the speed of voltage change at the gate (GN) of the field effect transistor (Q1) for reducing the speed of current change through the main current path of the field effect transistor (Q1) when the output signal (V.sub.o) changes from a first steady state (FST) via a transition area (TRE) to a second steady state (SST).

Abstract: A lateral DMOST with a drain extension 8 and a source contact entirely which overlaps the gate and thus forms a screen between the gate and the drain. The source contact 15 does not overlap the poly gate 9 but lies entirely laterally of this gate. The gate itself is provided with a low-ohmic metal contact strip 18, which results in a low gate resistance. A metal screening strip 20 is provided between this gate contact strip and the metal drain contact 16, which screening strip is connected to the source contact 15 next to the tips of the contact strip 18. Said screening strip leads to a major improvement in the power gain at high frequencies, for example in the RF range. The screening strip 20 may be realized together with the source, drain, and gate contacts in a common metal layer.

Abstract: The invention provides a method of combining an EPROM (or EEPROM) with a standard CMOS process. After growing the gate oxide 9, a lightly doped polycrystalline or amorphous silicon layer 10, hereinafter referred to as poly I, is deposited. In this layer, the floating gate 13 of the memory cells is defined, while, outside the memory matrix, the surface remains covered with poly I. Subsequently, the source/drain implantation in the memory cells is carried out. The poly layer 10 situated outside the memory matrix is masked against this heavy implantation by the mask 11. Subsequently, a second poly layer can be provided from which the control gates of the memory cells are formed and which forms a coherent layer with the existing poly I layer outside the matrix. In a subsequent series of steps in a standard CMOS process, the n-ch MOSTs and p-ch MOSTs are provided, n-type gates 22 for the n-ch MOSTs and p-type gates 23 for the p-ch MOSTs being formed from the poly I layer.

Abstract: A integrated circuit (100) includes a plurality of cores (110, 120). With each core (110, 120) is associated a TCB (112, 122) for controlling the core in a test mode thereof. Each TCB has a shift register (220) for holding test control data. The TCBs (112, 122) are serially linked in a chain (140) so that, the test control data can be serially shifted in. A system TCB (130) is provided in the chain (140) comprising a further shift register (220). The system TCB (130) is connected to each TCB (112, 122) for, after receiving a particular set of test control data in its shift register (220), providing the TCBs (112, 122) with a system test hold signal for switching between a shift mode and an application mode of the TCBs (112, 122).

Abstract: It may be necessary to provide conductors at very small distances from one another when electronic circuits, for example integrated circuits, are manufactured on an insulating substrate. A multilayer wiring system is often used in that case. The invention renders it possible to make very small inter-electrode gaps in a single conductor layer. To achieve this, the conductor layer is covered with a comparatively thick dielectric layer 4, 5 in which windows 8 are formed which extend over only part of the dielectric layer. Then an auxiliary layer 9 is provided which has depressions at the areas of the windows 8. Windows 11 are formed in the dielectric layer by anisotropic etching-back with dimensions which are substantially smaller than the dimensions of the original windows 8. The windows 11 may be used as etching windows or oxidation windows for the subsequent formation of the definitive conductor pattern.

Abstract: A flipflop, which is realized in an ECL or CML technique, has an internal output for the logic signal in a symmetrical mode and is provided with two transistor followers for supplying the two output signal components from the internal output, and each of these two transistor followers is one of the transistors of an enforcing pair, while the base of the other transistor is connected to a test signal input.

Abstract: A decoder for a memory cell which uses dynamic current to sense the conduction state of a memory cell. The decoder includes a sense circuit that is pre-charged from a voltage source. Upon disconnection of the sense circuit from the voltage source and connection of the memory cell to circuit ground via an access switch, the sense circuit is discharged if the memory cell is conductive and retains its charge if the memory cell is not conductive. The sense circuit outputs a signal indicative of the conduction state of the memory cell in dependence on whether the sense circuit is discharged or not. For low frequency operation, a weak feedback transistor maintains the sense circuit in the charged state after it is initially charged, and after connection to a memory cell if the memory cell is not conductive, to sustain the output signal and counteract the effects of the circuit leakage.

Abstract: A multi-coloured display unit is described for characters having colour indicator signals. The characters can be displayed in a plurality of colours. Without information of the identify of the characters getting lost, the legibility structure is influenced by the spreading of the colours over the various parts of the text. Initially, such colours are preselected when compiling the text. However, for various implementations this spreading is sub-optimal. Consequently, a transforming device is comprised for realizing and implementing a different colour structure and hence improving the legibility structure depending on the application and the original structure of the colour.

Abstract: A voltage converting multiplier circuit converts a single ended input voltage V.sub.gain into a differential output voltage V.sub.DO, and includes a differential input cell and a differential output cell, each biased by a respective control current. A control circuit includes an input device having a resistance R.sub.in coupled to an input terminal, and a differential amplifier which controls the differential input cell to maintain a voltage at one end of the input device equal to a reference voltage V.sub.REF, so as to convert the input voltage into an input current dI equal to (V.sub.REF -V.sub.in)/R.sub.1. A current mirror ensures that the input current is supplied by the branches of the differential input cell, which current splitting is mirrored to the differential output cell. An output device having a resistance R.sub.out in each branch of the differential output cell converts the differential output current to the differential output voltage V.sub.DO, where V.sub.DO =V.sub.in (R.sub.out /R.sub.in) (I.

Abstract: A battery management system 100 comprises input means 102 for receiving input signals, such as current or voltage, which represent a physical quantity of a battery. In operation, processing means 105 of the battery management system 100 calculate a physical quantity of the battery, such as the State of Charge, based on the input signals by using an electrochemical/physical model of the battery. The model includes a representation of a main electrochemical storage reaction, whose behaviour is calculated in dependence on a battery temperature. The processing means 105 calculates the battery temperature based on a temperature model of a temperature development in the battery. The battery management system 100 comprises output means 104 for outputting an output signal which is derived from a state of the electrochemical storage reaction. The battery management system 100 is, advantageously, used in a smart battery 10 or a battery charger/discharger 200.

Abstract: The data processing circuit has a self-timed instruction execution unit, which operates asynchronously, signalling the completion of processes and starting subsequent processes in response to such signalling. In order to satisfy real time constraints upon program execution ready signals generated after completion of selected instructions are gated with a timer signal before they are used to start a next instruction. In an embodiment, the amount of time left between the ready signal is used to start a next instruction is measured and used to regulate a power supply voltage of the instruction execution unit so that it is just high enough to make the instruction execution unit sufficiently fast to meet the real time constraints.

Abstract: A birectional transistor switch for large signal voltages comprises a first (T1) and a second (T2) transistor arranged in series, which are supplied with base current under command of a control signal in order to short-circuit a signal terminal (ST) to a reference terminal (RT) which is connected to the substrate of the circuit. When the transistor switch is open large negative voltage excursions of the signal (U) on the signal terminal (ST) will fire a thyristor formed by the first transistor (T1) and a parasitic transistor (TP) and thus cause an undesired short-circuit between the signal terminal and the reference terminal (RT). This is prevented in that under these conditions the node (N) between the two transistors is short-circuited to the reference terminal (RT), as a result of which the loop gain in the thyristor becomes so small that this thyristor is no longer fired.

Abstract: A current steering circuit includes a first current steering pair of differentially coupled transconductance devices for current steering an input current signal to an output of the current steering circuit. A linearizer circuit includes a second pair of differentially coupled devices coupled electrically in parallel with the first current steering pair so that any current steering which takes place in the second pair is mirrored by the first pair. The linearizer circuit controls the second differential pair so that the current through the devices of the second differential pair that are coupled to the output device of the first current steering pair is exponentially dependent on the differential input voltage.

Abstract: Starting from an input signal (data) and a clock signal (clk), this device supplies an output signal (CKREF0) identical to the input signal but resynchronized with the clock signal. It comprises two cascaded D-type flip-flops (63, 65), the clock signal of the second flip-flop being inverted (62) with respect to that of the first flip-flop. The first flip-flop has its output coupled to the data input of the second flip-flop via a multiplexer (64), which is controlled by a signal (d-Ph) containing information about the phase relationship between the input signal and the clock signal, in such a manner that either input signal or the signal from the first flip-flop is applied to the input of the second flip-flop. This device can be used in a known phase control loop comprising an oscillator whose frequency is controllable, a frequency divider, and a phase comparator.