Abstract: A nonvolatile memory device has a signature code generator generating an new signature code as a function of data read from the cell array and the previously calculated signature code. Data are read in sequence, using an internal clock generated by an internal clock oscillator. In test mode, the memory is scanned sequentially, beginning from any memory location, selected randomly, and the signature code is variable in dynamic way; at the end of memory scanning, the signature code is compared to an expected result. Thus, testing may be performed at Wafer Sort Test Level, reading the memory cells at the memory operative speed, so as to ensure an early, fast and thorough detection of faults.

Abstract: A ROM including an array, each cell of which is accessible by means of a column address and of a row address, includes a parity memory for storing the expected parity of each row and of each column, an electrically programmable one-time programmable address memory, a testing circuit for, during a test phase, calculating the parity of each row and of each column, comparing the calculated and expected parities for each row and each column, and in case they are not equal, marking the row or column in the address memory, and a correction circuit for, in normal mode, inverting the value read from the array cell, having its row and column marked in the address memory.

Abstract: A system and method for communication between a CPU and on-chip modules in an integrated circuit and off-chip devices is disclosed. A path on the integrated circuit allows for packet traffic to flow between the CPU and modules. In some embodiments the path is a data bus. Various types of packets are used, but each include a destination indicator to indicate the required destination device connected to the path. Data transfer packets are used for memory access operations. Normal event packets form prioritized interrupts wherein the recipient CPU or module respond to the event packet depending on relative priorities associated with other packets sent to the recipient device. Special event packets form command control signals that must be acted on by the recipient device when the special event packet is received.

Abstract: Self-aligned etching process for providing a plurality of mutually parallel word lines in a first conducting layer deposited over a plagiarized architecture obtained starting from a semiconductor substrate on which is provided a plurality of active elements extending along separate parallel lines e.g., memory cell bit lines and comprising gate regions made up of a first conducting layer, an intermediate dielectric layer and a second conducting layer with said regions being insulated from each other by insulation regions to form said architecture with said word lines being defined photolithographically by protective strips implemented by means of: a vertical profile etching for complete removal from the unprotected areas of the first conducting layer of the second conducting layer and of the intermediate dielectric layer respectively, and a following isotropic etching of the first conducting layer.

Abstract: An improved method and system for initializing the logical units (LUs) in a Gateway between an SNA network having a mainframe host computer and another network. An activation procedure derives the Table of Boundary LUs on the mainframe host computer by noting the device logical unit numbers within the set of ‘Activate Logical Unit’ (ACTLU) SNA Request Units. If the mainframe host computer includes an LU in its Table of Boundary LUs, then the activation procedure creates a corresponding LU in the Gateway. The activation procedure also marks each of the created LUs in the Gateway as active. The newly created LUs are then added to the resource pool of LUs available to the network.

Abstract: An improved method and system for initializing the logical units (LUs) in a Gateway between an SNA network having a mainframe host computer and another network. An activation procedure derives the Table of Boundary LUs on the mainframe host computer by noting the device logical unit numbers within the set of ‘Activate Logical Unit’ (ACTLU) SNA Request Units. If the mainframe host computer includes an LU in its Table of Boundary LUs, then the activation procedure creates a corresponding LU in the Gateway. The activation procedure also marks each of the created LUs in the Gateway as active. The newly created LUs are then added to the resource pool of LUs available to the network. Additional aspects include a method for assigning a logical unit type to an LU based upon whether a Bind request is received from the mainframe host computer within a certain amount of time after sending a positive sense code to the mainframe host computer.