Abstract: A technique for interpolating a series of samples includes constructing a mathematical model of the series that describes its large signal behavior. The model is subtracted from the original series to yield a residue. A discrete Fourier transform (DFT) is taken of the residue, and the DFT is zero-padded. An inverse DFT of the padded result yields an interpolated residue, which is then added back to the mathematical model to construct an interpolated version of the series of samples. Using this technique, accurate interpolation can generally be attained even when the series of samples is not coherently sampled.

Abstract: A switching topology for communicating signals in an automatic test system includes a plurality of switching circuits each for selectively passing signals or crossing signals. Switching circuits are connected together such that each node of any switching circuit connects to no more than one node of any other switching circuit. This topology offers improved signal integrity, reduced cost, and reduced space as compared with conventional, matrix-style switching topologies.

Abstract: Software is disclosed that creates a way of controlling alterations to cell contents of a data flow network so they can easily be turned on and off as separate layers. These layers can then be grouped as scenarios. Scenarios allow different layers of formula changes to be easily added and removed from the model.

Abstract: A low cost, low phase noise microwave synthesizer includes a DDS modulation circuit and a phase-locked loop. The DDS modulation circuit modulates the output of a DDS to a high frequency. The phase-locked loop downconverts the DDS output and locks the downconverted signal to a relatively low frequency, fixed reference.

Abstract: A technique for reducing errors in a PTIC (parallel, time-interleaved analog-to-digital converter) consisting of M ADCs involves sampling an input signal with the PTIC and performing M different DFTs, one for each ADC. Elements of the M DFTs are grouped together according to frequency and multiplied by correction matrices to yield a corrected, reconstructed power spectrum for the PTIC. The technique is especially effective at removing gain and phase errors introduced by individual ADCs of the PTIC, including gain and phase errors that vary with frequency.

Abstract: An ammeter for ATE instrumentation includes an amplifier, a first current measuring circuit coupled to the amplifier's power supply leads, and a second current measuring circuit coupled to the amplifier's output. The first current measuring circuit is used to select a desired current measurement range, away from the amplifier's output. Output transients caused by range changes are therefore avoided. The ammeter's response to load transients is also minimized, by providing smooth transitions between low current and high current operation.

Abstract: A high performance phase detector includes a local digital oscillator for generating a digital reference signal of programmable frequency and phase. The phase detector accumulates a difference in phase between the digital reference signal and a sampled input signal to produce a measure of phase error. The phase detector can be advantageously used in a frequency synthesizer to produce signals with low phase noise and accurate phase control. Synthesizers of this type can further be used to as building blocks in ATE systems and other electronic systems for generating low jitter clocks and waveforms.

Abstract: A technique for examining the frequency content of an analog signal includes sampling the analog signal using two analog-to-digital converters clocked at the same rate but offset with respect to each other by a delay. The technique involves computing a cross spectrum of one converter's output with respect to the other's. Owing to the delay between the converters, different frequencies of the analog signal are represented as different phases in the cross spectrum, thus allowing input frequencies to be inferred.

Abstract: A method for flexibly defining communication constructs includes providing at least one communication element type for at least one layer of a generalized communication model, such as a bus model. Each communication element type has a user-definable structure that is adaptable for representing a corresponding protocol layer of a target communication medium. Users can define specific communication element types to substantially represent the target protocol. Users can also define the communication element types to depart from the target protocol in precisely defined ways.

Abstract: A phase-locked loop (200) includes a sampler (202), a phase detector (210), a loop filter (212), and a VCO (214). The loop achieves frequency multiplication without the need for a divider in the loop's feedback path. The VCO (214) is operated above the Nyquist rate of the sampler, causing the loop to lock on an aliased signal. Any variations in the VCO output frequency (i.e., jitter or phase noise) are fed back to the phase detector (210) 1-for-1, without attenuation normally associated with frequency dividers. Loop gain can therefore be kept high, even in loops that provide high closed loop frequency multiplication. According to one variation, a harmonic generator (540) is placed between the VCO and the sampler, thus causing the loop to lock on harmonics of the VCO frequency. Open loop gain and precision are thus further improved.

Abstract: A system and method for configuring an automatic test system to produce a plurality of clocks from a reference clock includes a user interface and software. The user interface receives a plurality of inputs that specify desired frequencies of the plurality of clocks. In response to a command from the user interface, the software calculates values for dividers coupled to the reference clock, for deriving each of the desired frequencies from the reference clock. According to one embodiment, the desired frequencies form ratios that must be met to satisfy coherence. In calculating the divider values, the software minimizes frequency errors while precisely preserving the required ratios.

Abstract: A technique for pre-compensating a digital bit stream for distortion imposed by a transmission path includes adjusting the level of the digital bit stream on a bit-by-bit basis in a manner that simulates the effects of a filter having a transfer function that is substantially the inverse of that of the transmission path. The technique includes generating a plurality of reference levels that correspond to correcting levels of the digital bit stream and switching these levels to the transmission path at high speed in response to the current bit of the digital bit stream and at least one previous bit. When used in an automatic test system, the technique improves signal transmission and reduces jitter, therefore allowing jitter of devices under test to be measured more accurately.

Abstract: A system for positioning a test head for compliantly docking the test head with a prober, handler, or other peripheral for automatically testing electronic components. The system includes a plurality of backdrivable linear actuators. Each actuator has a first end mechanically coupled to the test head and a second end mechanically coupled to a support for holding the test head, for example, a manipulator. In a first mode, a control system applies inputs to the actuators for variably extending the actuators to establish a desired position of the test head relative to the support. The desired position is generally a centered position of the test head within a compliance range; however, it may also be a non-centered position that tends to align the test head with the peripheral. In a second mode, the control system stops varying the input to the actuator. The actuator tends to maintain its position, but complies with external forces applied to the test head.

Abstract: A probe tower for an automatic test system includes an insulative retainer for holding an array of differential probe assemblies. Each differential probe assembly is an elongated structure having first and second ends and first and second coaxial portions. Each coaxial portion includes an outer conductor and a pair of annular insulators positioned therein for holding a center conductor. First and second contact pins extend from the center conductor at the first and second ends, respectively. First and second ground pins, which are electrically connected to the outer conductors of the first and second coaxial portions, extend from the first and second ends for conveying ground connections.

Abstract: A technique for deskewing digitizer channels in an automatic test system includes applying a waveform of known frequency to the input of each digitizer channel. Each digitizer channel samples the waveform to produce a respective data record. A Discrete Fourier Transform (DFT), or a portion thereof, is then taken for each data record to determine, at minimum, the phase of the waveform. Phase differences across different digitizer channels are converted to time differences, which values are applied to subsequent digitizer measurements to correct for timing skew. Because a large number of samples in a digitizer's data record contribute to the computed phase of the waveform, the effects of timing jitter are substantially eliminated from skew measurements, without the need for repeating measurements and explicitly averaging results.

Abstract: A technique for determining the characteristics of an oscillatory test signal includes acquiring a plurality of consecutive samples of a test signal. The samples are mathematically fit to a sinusoidal model, which specifies a plurality of equations. The equations have unknowns that represent characteristics of a sinusoid that substantially intersects the plurality of samples. Solving the equations for the unknowns reveals the test signal's short-term characteristics.

Abstract: A circuit for generating one or more serial bit streams includes a memory coupled to a reformatter, which is in turn coupled to a serializer for converting parallel data to serial data. The memory includes a plurality of words having a known bit width (e.g., 32 bits) for storing one or more serial bit streams. The length of each serial bit stream is generally not an integer multiple of the memory's bit width, causing the last word storing each serial bit stream to contain a gap. The reformatter eliminates each such gap by combining bits from the last word of a bit stream with bits from the first word to provide a completely filled word to the serializer. As operation proceeds, the reformatter continues to combine bits from successive words to ensure that completely filled words are produced. Gaps that formerly appeared when producing serial bit streams are thereby eliminated.

Abstract: A cover attaches to a circuit board and has an inlet at one side for receiving forced air and plurality of openings on its top surface through which heat sinks mounted on the circuit board partially extend. Air is made to flow into the inlet and out the exhaust openings, thereby concentrating airflow in the vicinity of the circuit board's heat dissipative components.

Abstract: A system and method for capturing and evaluating high-speed serial data streams using conventional component testers includes a high-speed latching comparator coupled to the output of a device under test (DUT). The component tester stimulates the DUT to produce a high-speed serial data stream and strobes the latching comparator at predetermined instants of time relative to the serial data stream. In response, the latching comparator samples the digital state of the serial data stream and holds the sampled state. The component tester reads and stores the held state. The tester samples the serial data stream at multiple locations in this fashion, and takes multiple samples at each location. The tester averages the samples acquired at each location to render a probability function of the serial data stream verses time. The probability function has values that vary between zero and one, corresponding to the average value of the digital readings sampled at each point.

Abstract: A technique for determining the amplitudes of frequency components of a waveform sampled from an automatic test system includes assembling a list of N frequencies expected to be found in the sampled waveform. A test program running on the tester generally supplies the list of frequencies. The technique assumes that the sampled waveform conforms to an idealized waveform model that mathematically corresponds to a sum of N sinusoids. Each of the N sinusoids that make up the model has unknown amplitude and a frequency that equals one of the N frequencies in the list of frequencies. The technique attempts to solve for the unknown amplitude of each of the N frequencies by mathematically minimizing, via a linear least-squares algorithm, the difference between the model and the actual, sampled waveform.