Abstract: A processor in a data processing system having multiple cache memories performs cache memory or processor module affinity dispatchin. Processes awaiting dispatch are stored in prioritized queues. Each queue has a priority chain, and a chain for each cache memory or processor module, with each chain containing processes ready for dispatch. The dispatcher checks the queues in priority order, starting with the priority chain for a queue, followed by the chain corresponding to the cache memory or processor module that the process last executed upon, followed by chains corresponding to other cache memories or processor modules.
Type:
Grant
Filed:
September 23, 1999
Date of Patent:
December 16, 2003
Assignee:
Bull HN Information Systems Inc.
Inventors:
Jesse D. Hunter, Michel Brown, David A. Egolf, Jon Keil, Michael Meduna