Patents Represented by Attorney, Agent or Law Firm Burgees & Bereznak, LLP
  • Patent number: 6759289
    Abstract: A method for making a high voltage insulated gate field-effect transistor with multiple JFET conduction channels comprises successively implanting a dopant of a first conductivity type in a first substrate of a second conductivity type so as to form a first plurality of buried layers disposed at a different vertical depths. The first substrate is flipped over and then bonded to a second substrate of the first conductivity type. After the first substrate has been thinned, another set of implants are successively performed so as to form a second plurality of buried layers in stacked parallel relationship to the first plurality of buried layers.
    Type: Grant
    Filed: October 16, 2002
    Date of Patent: July 6, 2004
    Assignee: Power Integrations, Inc.
    Inventor: Donald Ray Disney