Abstract: A semiconductor-based optical phase-modulating device has first and second pairs of phase-fixing electrodes bracketing a pair of phase-modulating electrodes. The phase-fixing electrodes fix electric fields across end regions of the phase-modulating device to reduce distributed resistance and capacitance of the phase-modulating device, thereby improving the frequency response of the phase-modulating device. The optical phase-modulating device is particularly applicable to use in integrated optic Mach-Zehnder interferometers used for optical signal modulation.

Abstract: In methods and apparatus for encoding a repetitive analog waveform as m n-bit digital words, p analog samples of the repetitive waveform are taken at each of m distinct sampling points, and q bits are derived from each distinct sample, where m, n, p and q are positive integers, p and q are less than n, and p.times.q=n. The methods and apparatus employ novel methods and apparatus for generating a pulse train having a precisely controlled duty cycle to define sampling times at which the samples are taken. The encoding methods and apparatus are useful for encoding high speed waveforms with relatively low speed circuitry.

Abstract: In methods and apparatus for testing a digital system, scannable memory elements of the digital system are configured in a scan mode in which the memory elements are connected to define a plurality of scan chains. A test stimulus pattern is clocked into each of the scan chains at a respective clock rate, at least two of the clock rates being different from one another. The memory elements of each scan chain are then configured in a normal operation mode in which the memory elements are interconnected by the combinational network for at least one clock cycle at a highest of the respective clock rates. The memory elements are then reconfigured in the scan mode, and a test response pattern is clocked out of each of the scan chains at its respective clock rate. The methods and apparatus are particularly useful for testing digital systems such as digital integrated circuits in which different memory elements are clocked at different rates during normal operation.

Abstract: A phase lock loop comprises a voltage controlled oscillator, a phase detector and a loop filter comprising a charge pump and a filter network. The voltage controlled oscillator generates an output signal having a frequency which is responsive to a control voltage. The phase detector is responsive to the output signal and to a reference signal to generate a control signal indicative of a phase difference of the output signal and the reference signal. The charge pump is responsive to the control signal and to the control voltage to apply a charge indicative of both the phase difference and the control voltage to the filter network to develop the control voltage. Because the charge supplied by the charge pump depends on the control voltage as well as the phase difference of the output signal and the reference signal, the rate of adjustment of the output signal frequency depends on the present output signal frequency.

Abstract: A scan cell comprises a flip-flop, a mode selector and a weighting network. The mode selector responds to a mode-select signal by selectively applying a circuit data input signal or a scan data input signal to a data input of the flip-flop. The weighting network responds to one logic state of a weight-select signal by applying a circuit data signal substantially identical to a scan data output signal appearing at a scan data output of the flip-flop to a circuit data output. The weighting network responds to another logic state of the weightselect signal by applying a circuit data output signal having a predetermined ratio of occurrences of one logic state to occurrences of another logic state to the circuit data output. The scan cell is used for generating weighted random patterns in scan chains for scan testing digital systems.

Abstract: A self-testable digital integrator comprises binary adding apparatus and storage apparatus. The adding apparatus and the storage apparatus are functionally interconnected such that the storage apparatus feeds digital words to the adding apparatus for addition thereof and the adding apparatus feeds resulting digital words to the storage apparatus for storage thereof to perform a digital integration operation. The digital integrator further comprises a first combinational network responsive to a first state of a test mode signal to feed an external input signal to the adding apparatus for integration thereof, and responsive to a second state of the test mode signal to feed to the adding apparatus a test pattern signal derived from selected bias of the digital words fed from the adding apparatus to the storage apparatus.

Abstract: In a self-latching sense amplifier, a first pair of matched transistors is connected as a differential pair. A second pair of matched transistors is connected each to a respective one of the transistors of the first pair as a load transistor. A feedback circuit responsive to a differential output of the differential pair cross-couples the load transistors when the differential output is greater than a threshold value, and defeats cross-coupling of the load transistors when the differential output is less than the threshold value. The cross-coupling causes the output of the sense amplifier to latch. The sense amplifier is useful in memory circuits in which it is desired to shut down core components between memory operations to conserve power, and in other small signal detection circuits.

Abstract: A FET bidirectional switching arrangement comprises first and second FETs, and a limiting arrangement connected to the FETs. The FETs are operable in response to a first bias condition to pass current in series through the FETs in either of two opposite directions, and operable in response to a second bias condtion to block current through the FETs in both of the two opposite directions. The limiting arrangement senses the direction of current flowing through the FETs and limits a forward bias on a first pn junction of the first FET when the current flows in a first direction of the two opposite directions to limit undesired current flow through the first pn junction of the first FET. When the current flows in a second direction of the two opposite directions, the limiting arrangement limits a forward bias on a first pn junction of the second FET to limit undesired current flow through the first pn junction of the second FET.

Abstract: In an analog to-digital converter, an analog signal is applied to a signal node of a binary weighted capacitor array during a sampling interval to charge capacitors of the capacitor array. A reference voltage is selectively applied to individual capacitors of the capacitor array during a coding interval to redistribute charge among the capacitors and to thereby minimize a voltage at the signal node. A compensating signal responsive to transitions of an error producing signal is coupled to the signal node during the sampling and coding intervals. The bit pattern corresponding to the sample of the analog signal is determined from which capacitors of the array have the reference voltage applied thereto for minimizing the voltage at the signal node. The analog-to-digital converter is useful for codecs used in telephony applications for encoding and decoding voice signals and the like.

Abstract: Optical fiber joint loss is determined by launching an optical signal in an upstream fiber and measuring the launched signal at an end of the upstream fiber which is to be joined to a downstream fiber, joining the upstream fiber to the downstream fiber and disposing the joint in a transparent medium, the transparent medium having a refractive index substantially equal to or greater than a refractive index of a cladding of the downstream fiber, measuring a fixed proportion of optical power coupled at a predetermined angle with respect to a longitudinal axis of the downstream fiber immediately adjacent the joint, and estimating the optical fiber joint loss as L=1-k(P.sub.o /P.sub.i), where L is the estimated joint loss, P.sub.i is the optical power measured before making the joint, P.sub.o is the optical power measured after making the joint, and k is an empirically determined proportionality constant.

Abstract: An optical fiber connector element comprises a ferrule and an optical fiber stub secured within a through passage of the ferrule. The optical fiber stub comprises a core, an inner cladding having a diameter no more than six times the core diameter and a refractive index less than the core refractive index, and an outer cladding having a refractive index greater than the inner cladding refractive index and less than or equal to the ferrule refractive index. A length of the outer cladding is in intimate contact with the ferrule. A rearward part of the ferrule passage may have an inner diameter greater than the outer diameter of the fiber stub, and a plastic plug having a through passage for receiving the fiber stub may be located in the rearward part of the ferrule passage. The plastic plug has a refractive index equal to or greater than the outer cladding refractive index and less than the ferrule refractive index.

Abstract: In methods and apparatus for controlling the D.C. bias point of a nonlinear device, asymmetric envelope modulation is applied to an input signal, and the nonlinear device is driven by the asymmetric envelope-modulated signal and a D.C. bias signal. A nonlinear characteristic of the device is monitored at the modulation frequency, and the D.C. bias signal is controlled in response to the monitored characteristic so as to reduce the monitored characteristic at the modulation frequency. The methods and apparatus are particularly useful for controlling the D.C. bias point of semiconductor diode lasers, in which case the monitored characteristic can be the light output of the laser or the voltage across the laser.

Abstract: An optical fiber prooftester for exerting a controlled tensile force on spliced optical fibers includes a base member, a first optical fiber clamp in the form of a coil spring attached to the base and a sliding member mounted for movement on the base member. A second optical fiber clamp also in the form of a coil spring is fixed to the sliding member. A spliced optical fiber is mounted in the first and second clamps with the splice located between the clamps. A constant force wound spring acting between the base member and the movable member urges the movable member away from the first optical fiber clamp thereby applying a predetermined tensile force upon the splice.

Abstract: A differential amplifier includes a bias current source and a current dividing circuit for controllably dividing a bias current between first and second current paths. A first pair of matched transistors is connected as a differential pair between matched load impedances and the first current path. A second pair of matched transistors is connected as a differential pair between the matched load impedances and the second current path. Differential inputs of the second differential pair are connected to corresponding differential inputs of the second differential pair. The transistors of the first and second pairs have different emitter areas. Matched capacitors may be connected between respective differential inputs and differential outputs of the differential amplifier. The load impedances may be tapped to provide outputs having a lower differential gain. The differential amplifier is useful for building resonant circuits, for example voltage controlled oscillators having high Q factors.

Abstract: A resonant circuit comprises first and second amplifiers. An input of the second amplifier is coupled to an output of the first amplifier, and an output of the second amplifier is cross-coupled to an input of the first amplifier. The first amplifier has a first gain and a 90 degree phase shift between its input and its output at a resonant frequency of the resonant circuit. The second amplifier has a second gain and a 90 degree phase shift between its input and its output at the resonant frequency of the resonant circuit. The second gain is different from the first gain. The resonant circuit can have a first port and second ports coupled to an input and an output respectively of one of the first and second amplifiers. Because the gains of the first and second amplifiers differ, the gain from the first port to the second port of the resonant circuit will differ from the gain from the second port to the first port.

Abstract: An assembly for axially aligning two ferrules comprises a first housing, an alignment sleeve carrier, an alignment sleeve retained within a passage of the alignment sleeve carrier and a nut for securing the alignment sleeve carrier to the first housing such that a leading end of a first ferrule received in a passage of the first housing can extend into the alignment sleeve. The assembly further comprises a second housing, a socket member and a spring clip for securing the socket member to the second housing. The socket member has a through passage for receiving a second ferrule at one end and a leading end of the alignment sleeve carrier at another end such that the second ferrule can extend into the alignment sleeve for axial alignment with the first ferrule when the alignment sleeve carrier is received in the passage of the socket member.

Abstract: An optical fiber mechanical splice comprises a pair of gripping members and a resilient biasing member. Each gripping member has a plastically deformable griping surface. One of the gripping surfaces has a v-groove for receiving and aligning optical fiber ends. The resilient biasing means acts between the gripping members to resiliently bias the gripping surfaces of the gripping members toward one another. In use of the mechanical splice, the gripping surfaces are urged toward one another with optical fiber ends in abutting alignment in the v-groove. The gripping surfaces plastically deform around the fiber ends to provide a larger area of contact between the fiber ends and the gripping surfaces.

Abstract: In the monolithic integration of HFET and DOES device, a wide band gap carrier confining semiconductor layer is provided only at predetermined locations where DOES devices are desired. This layer is not provided at other predetermined locations where HFET devices are desired as it would constitute a shunt path which would degrade the high frequency operation of the HFET devices. The invention is particularly useful where monolithic integration of optical sources, optical detectors, and electronic amplifying or switching elements is desired.

Abstract: In methods and apparatus for aligning the phase of a local clock signal with the phase of a data signal, an incoming data signal is delayed to provide a delayed data signal and regenerated with a local clock signal to provide a regenerated data signal. A difference between the phase of the delayed data signal and the phase of the regenerated data signal is detected. The phase of the local clock signal is retarded by a predetermined fraction of a bit period if the regenerated data signal leads the delayed data signal and is advanced by the predetermined fraction of the bit period if the regenerated data signal lags the delayed data signal. The retiming, detecting, retarding and advancing steps are repeated continuously to obtain and maintain approximate alignment of the phase of the local clock signal with the phase of the delayed data signal. The methods and apparatus are useful in high speed packet switches.

Abstract: An optical waveguide is made by forming a layer of SiO.sub.2 on a substrate and implanting a region of the SiO.sub.2 layer with Si ions to define a region containing a stoichiometric excess of Si which defines a region having an elevated refractive index surrounded by a region having a lower refractive index. The resulting optical waveguide is stable at the high temperatures required for many semiconductor processing methods, and is useful for optical interconnection in integrated optical and optoelectronic devices.