Abstract: An improved sub-band speech coding system is provided by subdividing signals into a lower an higher subband, downsampling the lower subband before coding and coding the higher subband without downsampling. The decoder includes decoding and upsampling of the lower subband and decoding the higher subband and adding the higher subband to the lower subband.

Abstract: Estimation of the code size of variable length encoding of quantized DCT coefficients by summation over histogram bins of products of number of bin members and a code size of an average run of zero coefficients coupled with a representative level from the bin. The estimation provides low-complexity feedback for quantization level adjustment to obtain variable length code size target without actual performance of a quantization level plus variable length encoding.

Abstract: Linear predictive speech coding system with classification of frames and a hybrid coder using both waveform coding and parametric coding for different classes of frames. Phase alignment for a parametric coder aligns synthesized speech frames with adjacent waveform coder synthesized frames. Zero phase alignment of speech prior to waveform coding aligns synthesized speech frames of a waveform coder with frames synthesized with a parametric coder. Inter-frame interpolation of LP coefficients suppresses artifacts in resultant synthesized speech frames.

Abstract: Transcoding as from MPEG-2 SDTV to MPEG-4 CIF reuses motion vectors and downsamples in the frequency (DCT) domain with differing treatments of frame-DCT and field-DCT blocks, and alternatively uses de-interlacing IDCT with respect to the row dimension plus deferred column downsampling for reference frame blocks.

Abstract: A method of run-length encoding for known block size, such as image/video compression with block transform, such as DCT, with end of block indication suppressed when the end of the block can be inferred from the prior coding symbols.

Abstract: Computation of sprite position and size in JSR-184 with revised modelview matrix made with column vector lengths of original modelview matrix.

Abstract: Spread spectrum rake receiver estimates number of paths within a chip interval and assigns corresponding fingers. Cross-correlation matrix eigenvalues or direct BER estimates for differing numbers of fingers determine whether one or two fingers assigned to the group of paths within a chip.

Abstract: Automatic white balancing and/or autoexposure as useful in a digital camera extracts color channel gains from comparisons of image colors with reference colors under various color temperature illuminants and/or extracts exposure settings from illuminance mean, illuminance variance, illuminance minimum, and illuminance maximum in areas of an image with a trained neural network.

Abstract: Integer transforms of 4×4 blocks of the type used in proposed H.26L but adapted to 16-bit arithmetic by shifts after matrix multiplications and integer approximation matrices absorbing scaling factors.

Abstract: A DC-DC high frequency boost converter with a supply voltage input (110), a boosted voltage output (112), a series circuit of an inductor (114) and a rectifying device (116) connected in series between said supply voltage input (110) and said boosted voltage output (112), has a switch (124) connected between ground and a connection node (120) of said inductor (114) and said rectifying device (116). A control circuit (126) is provided for controlling said switch (124), and a zero inductor current detection circuit (128) is provided that compares a voltage (Un) on said connection node (120) with a reference voltage (Uref) and provides a zero inductor current indication (Comp) when both voltages are equal.

Abstract: Closed loop multiple-antenna wireless communications system with antenna weights determined by maximizing a composite channel signal-to-interference-plus-noise ratio minimum. Multiplexed symbol streams over subsets of antennas enhance throughput.

Abstract: An image coding method using wavelet decomposition and coding clusters of four-children coefficients bitplane-wise including value-bits for significance and refinement, and tree-bits for tree structure significance.

Abstract: A digital sigma-delta modulator requiring minimal die area and dissipating minimal power is formed with a plurality of integration stages coupled in tandem between an input node and an output node. The bit width of signals in the integration stages is progressively reduced from the first to the last integration stage without compromising modulator accuracy. A quantizer between the last integration stage and the output node provides the final reduction of signal bit width. The gain of the modulator feedforward and feedback paths are integer powers of two to further simplify the digital computation. In an exemplary implementation, three integration stages to form a third-order modulator are coupled in tandem between the input node and the output node. The gains of feedback and feedforward paths in one preferred embodiment are unity, and in some embodiments, one feedforward path has gain of 0.5.

Abstract: A loss-of-signal (LOS) detector includes a variable gain amplifier with an input receiving an input signal, a threshold comparator with a first input receiving a signal derived from an output of the variable gain amplifier, a second input receiving a reference level and an output providing a loss-of-signal indication signal. The variable gain amplifier has a gain control input receiving a gain control signal derived from the output of the threshold comparator and such that the gain of the variable gain amplifier is set to a lower value when the loss-of-signal indication signal is active, and set to a higher value when the loss-of-signal indication signal is not active. Accordingly, the LOS detector needs only one decision level for both of the LOS and NotLOS decisions, which is set in the linear range of the signal detector so that the hysteresis is reproduced precisely.

Abstract: Context-based adapative binary arithmetic coding (CABAC), as used in video standards such as H.264/AVC, with a renormalization of the interval low value plus range that includes partitioning of the bits of the low value to provide output bits plus low value update without bit-level iterations or aggregation of output bits until a full byte can be output.

Abstract: Decomposition of deblocking filters used in block-based video compression allows reduction of computational redundancies.

Abstract: A method and circuit for frequency synthesis using a low drift current controlled oscillator configured to provide a wide output frequency and high accuracy are provided. An exemplary frequency synthesis circuit is configured for programmable control of a center frequency of the current controlled oscillator to provide a wide range of output frequencies with high accuracy. In accordance with an exemplary embodiment of the present invention, an exemplary circuit comprises a phase-locked loop (PLL) circuit comprising a phase detector, a charge pump, a current controlled oscillator and a divider circuit. For programmable control of the current controlled oscillator, the PLL circuit further comprises a trim digital-to-analog converter (DAC) configured to provide a trimmed current signal for control of the current controlled oscillator.

Abstract: A frequency division multiplexing wireless transmission on two or more antennas with the set of symbols on subcarriers of a burst transmitted by one antenna transformed into another set of symbols on the subcarriers for the corresponding burst transmitted by another antenna. This helps overcome fading of the wireless channel by diversity.

Abstract: The present invention offers an optical disk determination circuit that can improve the stability of the operation to detect the peak (pulse signal) of the received light signal, and that can improve the stability of the optical disk determination operation. When determining the type of optical disk corresponding to the depth from the surface of the plane on which a light beam is irradiated to the data recording layer, light is irradiated while varying the focal position of the light beam at a constant velocity in one direction of the depth direction from the surface of the optical disk. The bottom level of the received light signal corresponding to the intensity of this reflected light is clamped at a specified level by the bottom clamp circuit 43. The received light signal with the bottom level clamped is compared with a specified reference voltage Vref by the comparator 45, and the received light signal peak (pulse signal) is detected corresponding to the results of this comparison.

Abstract: Apparatus and methods are disclosed herein that provide reduced bus transaction latency on a bus architecture that includes at least one master coupled to a plurality of slaves. As disclosed herein, a device (e.g., a slave) may include bus logic and host logic coupled to the bus logic. The bus logic may obtain a serialization token permitting the host logic to complete a transaction received by the bus logic via the bus. Further, the bus logic may keep the serialization token to complete at least one other transaction.