Abstract: A method (and structure) of forming a vertically-self-aligned silicide contact to an underlying SiGe layer, includes forming a layer of silicon of a first predetermined thickness on the SiGe layer and forming a layer of metal on the silicon layer, where the metal layer has a second predetermined thickness. A thermal annealing process at a predetermined temperature then forms a silicide of the silicon and metal, where the predetermined temperature is chosen to substantially preclude penetration of the silicide into the underlying SiGe layer.

Abstract: The method includes defining at least one sizing parameter for a capacitor arrangement (11). Once the parameter or parameters are defined, the method includes applying at least one sizing parameter to select a particular capacitor arrangement (11) for a free area on the integrated circuit chip (12). The selected capacitor arrangement comprises the largest arrangement which is accommodated within the free area, subject to the sizing parameter or parameters employed. Sizing parameters may include a height dimension range between a maximum and minimum height dimension for the capacitor arrangement, and permissible width dimensions for the capacitor arrangement. Steps in the layout method may be performed on a computer system (51) under the control of operational program code.

Abstract: A master-slave flip-flop circuit (200, 200′) includes a master latch circuit (202) and slave latch circuit (203). A hold control component (220) included in the master latch circuit (202) is interposed between a master latch node (ML) and a slave input node (SI). The hold control component blocks the transfer of data from the master latch node (ML) to the slave input node (SI) in response to a hold input. In the preferred form of the invention of the hold control component (220) comprises a tri-state inverter having an input connected to the master latch node (ML) and an output connected to the slave input node (SI). The hold input, comprising a high level hold signal and its complementary or inverted signal, disables the tri-state inverter and thus prevent data from being transferred from the master latch node (ML) to the slave input node (SI).