Patents Represented by Attorney Cathy L. Peterson
  • Patent number: 5892937
    Abstract: In a method and system for dynamically improving the performance of a server in a network, a tuning system monitors a workload of the server in real time, monitors a set of internal performance characteristics of the server in real time, and monitors a set of adjustable server parameters of the server in real time. The workload of the server may include the frequency and type of service requests received by the server from clients in the network. The internal server performance characteristics may include, for example, a data cache hit ratio of a data cache in the server. The set of server parameters may include, for example, the overall data cache size or the data cache geometry of the server. The tuning system periodically alters one or more of the set of adjustable server parameters as a function of the workload and internal performance characteristics of the server.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: April 6, 1999
    Assignee: Digital Equipment Corporation
    Inventor: Frank Samuel Caccavale
  • Patent number: 5835756
    Abstract: In a method and system for dynamically improving the performance of a server in a network, a tuning system monitors a workload of the server in real time, monitors a set of internal performance characteristics of the server in real time, and monitors a set of adjustable server parameters of the server in real time. The workload of the server may include the frequency and type of service requests received by the server from clients in the network. The internal server performance characteristics may include, for example, a data cache hit ratio of a data cache in the server. The set of server parameters may include, for example, the overall data cache size or the data cache geometry of the server. The tuning system periodically alters one or more of the set of adjustable server parameters as a function of the workload and internal performance characteristics of the server.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: November 10, 1998
    Assignee: Digital Equipment Corporation
    Inventor: Frank Samuel Caccavale
  • Patent number: 5822586
    Abstract: Apparatus and a related method for managing entities in a complex and, in general, geographically distributed system, such as distributed data processing system. The management approach is defined in terms of a generalized model having management modules integrated into a single cooperative system by a management director kernel. The management modules include presentation modules to provide an interface with users who manage the complex system, access modules to provide an interface with managed entities or devices, and function modules to define various functions that may be performed in controlling or monitoring the managed entities. If the complex system being managed is large, a managed entity and an associated access module may be located on one physical system, while a presentation module is located on another physical system, close to the user, and a function module being used might be located on yet another physical system, for reasons of processing convenience.
    Type: Grant
    Filed: September 4, 1996
    Date of Patent: October 13, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Colin Strutt, James Anthony Swist
  • Patent number: 5819033
    Abstract: In a method and system for dynamically improving the performance of a server in a network, a tuning system monitors a workload of the server in real time, monitors a set of internal performance characteristics of the server in real time, and monitors a set of adjustable server parameters of the server in real time. The workload of the server may include the frequency and type of service requests received by the server from clients in the network. The internal server performance characteristics may include, for example, a data cache hit ratio of a data cache in the server. The set of server parameters may include, for example, the overall data cache size or the data cache geometry of the server. The tuning system periodically alters one or more of the set of adjustable server parameters as a function of the workload and internal performance characteristics of the server.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: October 6, 1998
    Inventor: Frank Samuel Caccavale
  • Patent number: 5790775
    Abstract: Provided herein is a method and apparatus for host transparent storage controller failover and failback. A controller is capable of assuming the identity of a failed controller while continuing to respond to its own SCSI ID or IDs in such a way that all SCSI IDs and associated units (LUNS) of the failed controller are effectively taken over by the surviving controller. This "failover" behavior is transparent to any attached host computers and is treated by such attached hosts as a powerfail condition. The symmetric operation of returning the targets (IDs) and units (LUNs) to the previously failing controller ("failback") is likewise transparent.
    Type: Grant
    Filed: October 23, 1995
    Date of Patent: August 4, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Randal S. Marks, Randy L. Roberson, Diana Shen, Stephen J. Sicola
  • Patent number: 5774643
    Abstract: Disclosed is a method and apparatus for reconstructing data in a computer system employing a modified RAID 5 data protection scheme. The computer system includes a write back cache composed of non-volatile memory for storing (1) writes outstanding to a device and associated data read, and (2) storing metadata information in the non-volatile memory. The metadata includes a first field containing the logical block number or address (LBN or LBA) of the data, a second field containing the device ID, and a third field containing the block status. From the metadata information it is determined where the write was intended when the crash occurred. An examination is made to determine whether parity is consistent across the slice, and if not, the data in the non-volatile write back cache is used to reconstruct the write that was occurring when the crash occurred to insure consistent parity, so that only those blocks affected by the crash have to be reconstructed.
    Type: Grant
    Filed: October 13, 1995
    Date of Patent: June 30, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Clark E. Lubbers, Susan G. Elkington, Ronald H. McLean
  • Patent number: 5761501
    Abstract: Disclosed herein is a stacked skip list data structure for maintaining select nodes on multiple lists. The data structure includes a primary and a secondary skip list of nodes. Each node in the primary skip list uses at least one forward pointer in a primary array of forward pointers and provides a node level field for storing the level of such node, the level determined by the number of pointers being used. A secondary skip list is stacked on the primary skip list of nodes. It includes a subset (zero or more nodes) occurring on the primary skip list and utilizes zero or more unused forward pointers in the primary array as its forward pointers. Thus, a system agent performing operations on the secondary skip list utilizes the node level in the node level field as an index into the primary array of forward pointers to locate the secondary array of forward pointers.
    Type: Grant
    Filed: October 2, 1995
    Date of Patent: June 2, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Clark E. Lubbers, Susan G. Elkington
  • Patent number: 5742819
    Abstract: In a method and system for dynamically improving the performance of a server in a network, a tuning system monitors a workload of the server in real time, monitors a set of internal performance characteristics of the server in real time, and monitors a set of adjustable server parameters of the server in real time. The workload of the server may include the frequency and type of service requests received by the server from clients in the network. The internal server performance characteristics may include, for example, a data cache hit ratio of a data cache in the server. The set of server parameters may include, for example, the overall data cache size or the data cache geometry of the server. The tuning system periodically alters one or more of the set of adjustable server parameters as a function of the workload and internal performance characteristics of the server.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: April 21, 1998
    Assignee: Digital Equipment Corporation
    Inventor: Frank Samuel Caccavale
  • Patent number: 5737546
    Abstract: Bus interfaces for nodes coupled to a system bus in a computer system, the system bus including an address bus and a separate data bus. System bus operations include address and command transactions and data transactions. Data transactions occur on the data bus separately and independently of the occurrence of address and command transactions on the address bus. A bus interface may include any of a commander address bus interface means for providing to an address bus address and command transactions, a responder address bus interface means for acknowledging receipt of address and command transactions via the address bus, a commander data bus interface means for controlling submission to the data bus of data transactions as a result of the occurrence of address and command transactions on the address bus, and a responder data bus interface means for transferring data on the data bus during a data transaction.
    Type: Grant
    Filed: December 31, 1996
    Date of Patent: April 7, 1998
    Assignee: Digital Equipment Corporation
    Inventors: David M. Fenwick, Denis J. Foley, Stephen R. Van Doren, Dale R. Keck
  • Patent number: 5734659
    Abstract: A system has a node connected to a network, the node generating a separate session message for each of a plurality of users. The node places each of the separate session message in a slot in a single virtual circuit message, and transmits the virtual circuit message onto the network. A server is connected to the network, and the server receives the virtual circuit message, and the server identifies each of the separate session messages. The server then transmits each of the separate session message to a user having a session corresponding to each of the separate session messages.
    Type: Grant
    Filed: April 1, 1994
    Date of Patent: March 31, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Bruce Mann, Darrell Duffy, Anthony Lauck, William Strecker
  • Patent number: 5732240
    Abstract: In a method and system for dynamically improving the performance of a server in a network, a tuning system monitors a workload of the server in real time, monitors a set of internal performance characteristics of the server in real time, and monitors a set of adjustable server parameters of the server in real time. The workload of the server may include the frequency and type of service requests received by the server from clients in the network. The internal server performance characteristics may include, for example, a data cache hit ratio of a data cache in the server. The set of server parameters may include, for example, the overall data cache size or the data cache geometry of the server. The tuning system periodically alters one or more of the set of adjustable server parameters as a function of the workload and internal performance characteristics of the server.
    Type: Grant
    Filed: November 27, 1996
    Date of Patent: March 24, 1998
    Assignee: Digital Equipment Corporation
    Inventor: Frank Samuel Caccavale
  • Patent number: 5724539
    Abstract: A method and apparatus for bandwidth balancing of data transfer operations between a computer and a storage subsystem are disclosed. The storage subsystem contains a number of storage devices such as magnetic disk drives. Data to be stored is supplied by the computer to the storage subsystem in the form of a transfer unit through a communication channel. The storage subsystem divides the transfer unit into a number of stripes of a pre-determined size. Each stripe is allocated to a separate disk drive whose disk surfaces are formatted into a number of track bands. Each track band is composed of several contiguous tracks associated with the same data transfer rate. Each stripe is then stored on its disk drive within a selected track band. Both data storage and retrieval from each disk drive occur at the data transfer rate associated with the accessed track band.
    Type: Grant
    Filed: April 5, 1994
    Date of Patent: March 3, 1998
    Assignee: Digital Equipment Corporation
    Inventors: Charles Michael Riggle, Bruce D. Buch
  • Patent number: 5684944
    Abstract: A method for atomically updating Error Detection Code (EDC) protected data in memory such that the EDC protection is maintained to the granularity of a single microprocessor machine instruction. The method is employed in a memory system having a volatile storage area and at least one nonvolatile storage area, each of the storage areas storing a copy of the protected data and two copies of its associated error detection code. The volatile and nonvolatile storage areas each have a first storage location for storing one of the copies of the associated error code and a second storage location for storing the other of the copies of the associated error code. In such a system, a chosen field with the data structure in the volatile copy is updated. Once the volatile copy is updated, a new error detection code is computed with the data in the volatile copy. The new error detection code is then written to the first storage location in each of the storage areas, volatile and nonvolatile, one at a time.
    Type: Grant
    Filed: August 14, 1995
    Date of Patent: November 4, 1997
    Inventors: Clark E. Lubbers, Susan G. Elkington
  • Patent number: 5671406
    Abstract: An apparatus and method for performing a skip list insertion sort on a singly linked list of elements is provided. Each element to be sorted includes a key, an element pointer in an element pointer field and a flag bit. Also provided is an indexed array of pointer arrays. If an element is to be inserted at a node level greater than zero, a free pointer array is allocated by storing an index corresponding to the allocated pointer array in the element pointer field and setting the corresponding flag bit. If a free pointer array is not available, then the node level of the element is forced to zero. If the level of the element is either assigned as or forced to zero, the flag bit is not set and the pointer array itself occupies the element pointer field as the element pointer instead of the index. Thus, the pointer to the element pointer field will point directly to the specified pointer array location without having to index into the array of pointer arrays.
    Type: Grant
    Filed: October 18, 1995
    Date of Patent: September 23, 1997
    Assignee: Digital Equipment Corporation
    Inventors: Clark E. Lubbers, Susan G. Elkington
  • Patent number: 5666551
    Abstract: A data bus sequencer for use by nodes coupled to a system bus for associating data transactions and address transactions on the bus. A mechanism for tracking address and command transactions occurring on the bus produces, for each address and command transaction occurring on the address bus, a corresponding sequence number tag. Those sequence number tags corresponding to address and command transactions for which data transactions are to be initiated by the node are stored by the data bus sequencer. The data bus sequencer further includes circuitry for counting the number of data transactions occurring on the data bus, comparing the counted number of data transactions to the stored sequence number tags and initiating data transactions on the data bus in response to the comparison.
    Type: Grant
    Filed: January 24, 1996
    Date of Patent: September 9, 1997
    Assignee: Digital Equipment Corporation
    Inventors: David M. Fenwick, Denis J. Foley, Stephen R. Van Doren, David W. Hartwell, Elbert Bloom, Ricky C. Hetherington
  • Patent number: 5664221
    Abstract: A system for assigning addresses to devices interconnected on a small computer system interface (SCSI) bus. A device address bus independent of the SCSI bus interconnects address assignable devices on the SCSI bus. The devices, each of which has a SCSI ID by which it is identified and being set with default bus address information representing the SCSI ID, are connected to one or more address lines on the device address bus. A system user can selectively reconfigure the bus addresses of the devices by utilizing a personality unit to override one or more bits of the bus address information. The personality unit includes a bus address selector, coupled to the device address bus, which selects address lines according to user input. The selecting of an address line effects a change in the default bus address information associated with the one or more devices connected to the selected address line.
    Type: Grant
    Filed: November 14, 1995
    Date of Patent: September 2, 1997
    Assignee: Digital Equipment Corporation
    Inventors: Mark F. Amberg, William K. Miller, Frank M. Nemeth, Dwayne H. Swanson
  • Patent number: 5659739
    Abstract: A system and technique for optimizing the efficiency of maintenance operations performed on skip lists of data elements or nodes stored in memory is provided. Each node of a skip list includes a back pointer for pointing to an immediate predecessor node and a node level field for recording the node level associated with the node. The system further includes a system agent for operating on the data structure, the system agent capable of locating the address of the immediate predecessor node pointing to a selected node by using the back pointer in the selected node.
    Type: Grant
    Filed: October 2, 1995
    Date of Patent: August 19, 1997
    Assignee: Digital Equipment Corporation
    Inventors: Clark E. Lubbers, Susan G. Elkington, Richard F. Lary
  • Patent number: 5652837
    Abstract: The invention provides a new process and apparatus for generating and selectively processing command requests issued over a bus. Command requests are generated by devices, each of which may be authorized or not authorized to cause the execution of the requested command. A unique identifier is provided for each device. The command requests are received and the identity of the device which issued the command request is determined. The command is then executed only if the unique identifier associated with the requesting device indicates that the device is authorized to cause the execution of the requested command.
    Type: Grant
    Filed: October 13, 1995
    Date of Patent: July 29, 1997
    Assignee: Digital Equipment Corporation
    Inventors: Nicholas Allen Warchol, Chester Pawlowski