Patents Represented by Attorney, Agent or Law Firm Charles A. Mirho
  • Patent number: 6351783
    Abstract: A method includes setting a contention scheme for an asynchronous bus such that the contention delay of isochronous transactions on the asynchronous bus is bounded. A first device is coupled to the asynchronous bus to receive an isochronous transaction from an isochronous device and output the isochronous transaction to the asynchronous bus. A second device is coupled to the asynchronous bus to receive the isochronous transaction from the asynchronous bus and output the isochronous transaction to a third device.
    Type: Grant
    Filed: May 20, 1999
    Date of Patent: February 26, 2002
    Assignee: Intel Corporation
    Inventors: John I. Garney, Brent S. Baxter
  • Patent number: 6219264
    Abstract: A method includes producing a control voltage signal that exceeds a rated maximum control voltage signal level for a switch, and limiting the control voltage signal applied to the switch to no greater than the rated maximum control voltage signal level.
    Type: Grant
    Filed: July 29, 1999
    Date of Patent: April 17, 2001
    Assignee: Intel Corporation
    Inventor: Josef C. Drobnik
  • Patent number: 6130680
    Abstract: A computer graphics system for caching textures includes an L3 memory, an L2 cache, and an L1 cache for storing such textures and also includes a graphics accelerator (GA) for mapping these stored textures onto primitives for graphics display. The L3 memory, which has the largest capacity also has the slowest retrieval speed, while the L1 cache has the smallest capacity and the quickest retrieval speed. The textures are divided into a plurality of L2 texture blocks and each L2 texture block is subdivided into a plurality of L1 sub-blocks. During its rendering process, the GA searches the L1 cache for a particular L1 sub-block that is to be applied to a primitive. If such L1 sub-block is stored within the L1 cache, the GA will extract the desired texels (i.e., texture pixels) from the L1 sub-block and apply such texels to the primitive. If the L1 sub-block is not located in the L1 cache, the GA will search the L2 cache for the L1 sub-block.
    Type: Grant
    Filed: December 1, 1997
    Date of Patent: October 10, 2000
    Assignee: Intel Corporation
    Inventors: Michael Brian Cox, Michael J. Shantz
  • Patent number: 6108772
    Abstract: A numerical processing method on a computer system in which an instruction having at least one operand and a type control is retrieved, and the operand is converted to a precision specified by the type control. The instruction is executed in the precision specified by the type control to obtain a result, and when the destination precision differs from the precision specified by the type control, the result is converted to the destination precision using a second instruction.
    Type: Grant
    Filed: June 28, 1996
    Date of Patent: August 22, 2000
    Assignee: Intel Corporation
    Inventor: Harsh Sharangpani
  • Patent number: 6065105
    Abstract: In a microprocessor, an instruction scheduler 30 includes a dependency matrix 36 and a waiting buffer 34. A dependency determination unit 32 receives instructions to be executed, forwards the instructions to the waiting buffer 34, determines if any dependency exists between the instructions, and forwards the dependency information to the dependency matrix 36 in the form of a dependency vector 40. The dependency matrix 36 periodically determines whether any of the instructions contained in the waiting buffer 34 are ready to be executed, that is, no dependencies exist for that instruction. As each instruction is dispatched for execution from the waiting buffer 34, the dependency vector 40 for all dependent instructions is cleared for subsequent execution. In this manner, an out-of-order processing scheme is implemented that efficiently accounts for data dependency between processed instructions.
    Type: Grant
    Filed: January 8, 1997
    Date of Patent: May 16, 2000
    Assignee: Intel Corporation
    Inventors: Nazar Zaidi, Gary Hammond, Ken Shoemaker, Jeff Baxter
  • Patent number: 6041364
    Abstract: A method and system for adding device entries to a device tree is disclosed. When the computer system detects the connection of a device, the computer system searches a device tree to determine if the device is being connected for the first time. If so, a device entry for the device, including a device type and at least one device function, is added to the device tree. Using the device type and at least one device function, the system searches a match tree to identify at least one first sequence of instructions to execute when the device is connected for the first time. The first sequence of instructions modifies the device entry to associate at least one software category with the device. The first sequence of instructions may: (1) modify the device entry to include at least one software component to be notified when the device is connected; and/or (2) modify the device entry to associate with each software category at least one software component to be used with the device.
    Type: Grant
    Filed: December 19, 1996
    Date of Patent: March 21, 2000
    Assignee: Intel Corporation
    Inventors: Victor Lortz, Stephen T. Chou