Abstract: A capacitor of a semiconductor memory device having a greater cell capacitance than a double-cylindrical capacitor and an improved method for manufacturing the same are disclosed. A first conductive layer is formed on a semiconductor substrate and then first and second material layers are formed on the first conductive layer. The first material and second material layers are patterned to form a composite pattern comprised of a precursory first material pattern and a second material pattern. The precursory first material pattern is anisotropically etched to form a first material pattern smaller than the second material pattern. Here, an undercut portion under the second material pattern is created. Then, the first conductive layer is anisotropically and partially etched to form a first conductive layer pattern having a groove defining a protruding stepped portion into an individual cell unit.

Abstract: A semiconductor SRAM device is provided wherein the electrical characteristics of the memory cell of the SRAM device is enhanced by decreasing the OFF-current and by increasing ON-current of PMOS thin film transistor (TFT) load elements. An offset region is formed between the drain and channel regions of the PMOS TFT. The gate is formed below (or above) the channel region of the PMOS TFT, and an insulating layer is formed below the gate. A ground potential V.sub.ss conductive layer is formed below the insulating layer, facing the offset region, to thereby operate as a gate for the offset region. The ground potential of the conductive layer facing the offset region of the PMOS TFT is constantly ON because of the gate operation of the ground potential conductive layer. A higher ON/OFF current ratio results, and the electric characteristics of the PMOS TFT load elements and therefore the SRAM device are thereby enhanced.

Abstract: A peripheral/refresh control circuit for a semiconductor memory device, e.g., a dynamic random access memory (DRAM), which includes a first pull-up device connected between a supply voltage and the pull-up node of a sense amplifier, the first pull-up device having a first mode of operation wherein the power supply voltage is coupled to the pull-up node and a second mode of operation wherein the power supply voltage is isolated from the pull-up node, a second pull-up device coupled between a boosting voltage and the pull-up node, the second pull-up device having a first mode of operation wherein the boosting voltage is coupled to the pull-up node and a second mode of operation wherein the boosting voltage is isolated from the pull-up node, a first pull-up control circuit for selectively switching the first pull-up device between its first and second modes of operation, and a second pull-up control circuit for selectively switching the second pull-up device between its first and second modes of operation.

Abstract: An SRAM memory cell structure is provided which has the access transistor gates formed from a different layer than that of the word line. The first access transistor gate of a first memory cell is connected to the first access transistor gate of an adjacent second memory cell, and a second access transistor gate of the first memory cell is connected to a second access transistor gate of an third oppositely adjacent memory cell. Each pair of coupled gates are formed separate from the access transistor gates in adjacent memory cells. The word lines connect the separated access transistor gates. The word lines are formed on an insulating layer above the gates of the access transistors. The word lines are, however, electrically connected to the gates of the access transistors through contact holes formed in the insulating layer. Each memory cell is arranged symmetrically with respect to an adjacent memory cell, and the components of each memory cell are symmetrical.

Abstract: A surface mount semiconductor package having a novel lead configuration which facilitates a higher packing density than presently available semiconductor packages. More particularly, the package includes a plurality of electrical leads each having a laterally outwardly extending portion, a downwardly extending portion depending from an inner distal end of the laterally extending portion, and a foot portion extending laterally inwardly from a lower distal end of the downwardly extending portion. A semiconductor chip is mounted, preferably by adhesive means such as insulating tape, to the foot portion of the leads. A plurality of electrical wires are connected between an upper surface of the chip and the laterally outwardly extending portion of respective ones of the leads. A protective body, such as a molded resin body, encapsulates the chip, the wires, the laterally outwardly and downwardly extending portions of the leads.

Abstract: A mask ROM having a defect repairing function stores address signals corresponding to a defective memory cell and then, selectively activates either a redundancy row decoder or a row decoder according to whether the address signals stored are identical to address signals supplied externally. The mask ROM includes first and second memory cell arrays formed by grouping in a word line direction a plurality of read only memory cells arranged in rows and columns; first and second row decoders for combining row address signals supplied externally so as to selectively drive the word lines of the first and second memory cell arrays; and a row decoder selector for storing therein address signals according to a row block including a defective memory cell, of the first memory cell array so as to inactivate the first row decoder and activate the second row decoder when the external row address signals are equal to the address signals stored in the row decoder selector.

Abstract: A charge-coupled device (CCD) is provided having improved charge transfer efficiency. This CCD is a portion of an image sensor and manufactured by first laminating a first oxidation film and a first nitride film one after the other on a semiconductor substrate and then forming a plurality of first gate electrodes on the first nitride film at predetermined intervals apart. A second oxidation film is formed only on an upper surface and along side walls of each of the first gate electrodes. The first nitride film exposed between the first gate electrodes is removed and a second nitride film is formed on the exposed first oxidation film and the second oxidation film. A second gate electrode is then formed on the second nitride film between adjacent first gate electrodes. An image sensor is obtained in which leakage current density between the gate electrodes is reduced and the dielectric characteristic of a gate dielectric film is improved.

Abstract: A semiconductor diode characterized by an anode electrode structure connected to a double diffusion of P-type impurities in a major surface of an N.sup.- semiconductor. The first diffusion forming a first plurality of P.sup.- well regions and the second diffusion selectively forming a second plurality of P.sup.+ well regions within the first well region.

Abstract: A stereo and dual audio signal identifying system comprising, an FM detector, bandpass filter, and AM detector which generate a filter/detected input to a first PLL having a 210 Hz reference signal. The first PLL generates a first input to a comparator and a second PLL generates a second input to the comparator. The comparator generates an output signal indicative of the presence of stereo and dual audio signals.

Abstract: An LOC type semiconductor package and a fabricating method thereof comprises first and second through holes formed at inner leads and bus bars of the LOC-type lead frame, and third through holes formed at the tape which is bonded with the lower side of the inner leads and the bus bars, by pins at a tape cutter. Thus, air existing at both tape during the bonding process effectively flows out so as to prevent the trapping of air bubbles. Accordingly, during the wire bonding process, wire shorting and damage to the package body can be prevented. Since EMC is deposited into the first and the second through holes and supports the inner leads and the bus bars during the molding of the semiconductor package, the reliability of the semiconductor package can be improved.

Abstract: A circuit is provided for protecting the internal circuit of a semiconductor device from electrostatic discharge (ESD). This circuit includes an input pad for applying an input signal to the internal circuit, a metal line for electrically connecting the input pad and internal circuit. This metal line has at least one RC delay stage caused by inherent parasitic resistances and capacitances. Also, a punch-through element is provided to connect the metal line to a ground voltage terminal disposed between the input pad and a delay stage. Finally, a resistor is used to connect the at least one delay stage to the internal circuit.

Abstract: A method for forming a mask pattern using a multi-layer photoresist film process is disclosed. The processing is simplified from known processes by using a silylated photoresist film. A first photoresist layer is formed on substrate and part of the surface of the photoresist layer is silylated to thereby form a silylation layer. Then, a second photoresist layer is formed on the silylation layer, which is then exposed through the photo mask having a predetermined pattern. A second photoresist pattern is then formed after development. Then, a silylation layer pattern is formed by etching-back the silylation layer using the second photoresist pattern as an etching mask. The silylation pattern is then oxidized, and the first photoresist layer is etched using the oxidized silylation pattern, thereby forming a first photoresist pattern. A resolution increasing effect can be maintained using the two layer photoresist film structure without the need for an intermediate oxide film.

Abstract: Disclosed is a semiconductor device wherein the down bonding and the mounting of multi-pin is made possible. A conductive member adhered to the bottom surface of the semiconductor element. The conductive member and the specific pad of the semiconductor element are connected by the connecting member, which enables the entire bottom surface of the semiconductor element to be used for down bonding. Further, the more effective latch-up suppression, noise dispersion and speed improvement compared with the conventional LOC-type package structure is possible.

Abstract: A manufacturing method for a semiconductor memory device including a capacitor having a double fin-shaped structure is provided, wherein a storage electrode is formed by applying a thick planar material capable of being wet-etched between the double fins consisting of conductive layers. The storage electrode is formed by forming a thin, high temperature oxide film having an etching rate which is great. Thus, the resulting memory cell's topography is improved and damage to the storage electrode is decreased.

Abstract: A serial data port in a dual port memory device adapted to receive incoming serial data and transfer the incoming serial data to a general data register, comprising; a plurality of data latches storing a portion of the incoming serial data, each data latch comprising a plurality of shift registers, and each shift register being responsive to one of a plurality of sequentially generated shift register control signals, and a plurality of transfer gates, each transfer gate gating the incoming serial data into a corresponding data latch in responsive to a one of a plurality of sequentially generated data latch control signals, wherein each data latch control signal defines a time period, and the plurality of shift register control signals is sequentially generated within the time period.

Abstract: A method for manufacturing a bump on a semiconductor comprising the steps of: forming metal pad on a portion of a surface of a substrate, forming a barrier metal layer over the surface of the substrate such that the barrier metal layer cover the metal pad, forming a photoresist layer over the barrier metal layer, forming an opening in the photoresist layer to expose a portion of the barrier metal layer overlaying the metal pad, forming a chip bump in the opening, selectively removing the photoresist layer using the bump as a mask, such that residual portions of the photoresist layer remain, and such that portions of the barrier metal layer are exposed, etching the exposed portions of the barrier metal layer using the residual photoresist layer as a mask, and removing the residual photoresist layer.

Abstract: The present invention relates to a write signal input buffer, among input buffers of semiconductor memory device, for receiving a write enable signal supplied from the exterior of chip. The present invention provides a write signal input buffer at least having an input stage for receiving a write enable signal supplied from the exterior of chip, logic means for generating a write drive signal as a correspondence signal according to an output signal of the input stage, and a latch portion for latching an output signal of the logic means and including switching means controlled by a drive signal of data output stage circuit on its latch path. Accordingly, normal driving operation is carried out according to input of external write enable signal regardless of the ground noise induced in data output operation, thereby guaranteeing a correct write operation of chip.

Abstract: A liquid crystal display device includes laminated plural electrical field effect type liquid crystal layers with light-transmitting electrically insulating layers inserted therein, and liquid crystal injection holes for forming the columns for supporting the insulation layers and the liquid crystal layers. The structure of the liquid crystal display device is changed in the manner that the columns are striped so as to increase the width thereof and the liquid crystal injection holes are rod-shaped so as to increase the section width thereof. Accordingly, the gap of the liquid crystal layers is maintained and the etching time for dissolution layers is considerably reduced, thereby improving the structural quality of the liquid crystal display device and obtaining a uniformly displayed image.

Abstract: A digital servo system for servo controlling a prescribed function of a host device, e.g., the tracking servo function of an optical disk drive. The digital servo system includes a variable gain amplifier for amplifying an analog error signal issued by the host device, an A/D converter for converting the analog error signal to a digital error signal, an adder for adding a wobbling signal to the digital error signal to produce a composite digital error signal, digital signal processing circuitry for processing the composite digital error signal to produce a processed digital error signal, a D/A converter for converting the processed digital error signal to an analog servo control signal to be used in servo controlling the prescribed function of the host computer.