Patents Represented by Attorney, Agent or Law Firm Cheate, Hall & Stewart
  • Patent number: 6650014
    Abstract: A semiconductor device has a plurality of bump electrodes for external connection arrayed two-dimensionally on the surface of a semiconductor chip where the desired elements and wirings are formed. The bump electrodes include a first group of bump electrodes, a second group of bump electrodes arrayed at the outer periphery of the first group of bump electrodes, and a third group of bump electrodes, arrayed at the outer periphery of the second group of bump electrodes. The first and second groups of bump electrodes are arrayed in a grid with intervals Sx1 in the X direction and Sy1 in the Y direction. The third group of bump electrodes has a structure satisfying Sx2>Sx1 and Sy2>Sy1, where Sx2 and Sy2 are orthogonal intervals for the third group of bump electrodes along axes diagonal to axes of intervals of the first and second groups of bump electrodes.
    Type: Grant
    Filed: June 13, 2002
    Date of Patent: November 18, 2003
    Assignee: NEC Electronics Corporation
    Inventor: Shuuichi Kariyazaki