Abstract: A method of fabricating sub-micrometer gates in a semiconductor device is disclosed in which a pre-passivation layer is formed over the gate region during fabrication. This pre-passivation layer protects the gate and underlying gate trough region from surface contamination during device fabrication. Sub-micrometer gate lengths are obtained by use of optical lithography, e.g., angle-shadow metal evaporation techniques and chemical lift-off methods.

Abstract: Regular arrays of grain boundary free silicon islands have been produced in a silicon on insulator (SOI) structure by using a pattern antirelfective coating in combination with a laser scanning technique. The antireflective coating pattern is made up of a series of parallel stripes terminating in seeding windows. A laser beam is scanned perpendicular to the stripes and over at least two stripes simultaneously, with the long axis of the beam parallel to the scan direction. Grain boundaries are confined to the region under the antireflective stripes.

Abstract: A method for planarizing dielectric films between conductive layers on semiconductor wafers is disclosed. Two successive dielectric layers are deposited over a pattern on a wafer and coated with a polymer which has a substantially flat surface. Planarization is obtained when the wafer is plasma etched with the etch rate of the polymer equal to the etch rate of the second dielectric layer. The etch is stopped when all of the polymer has been removed from the wafer. Selectivity in etch rates between the first and second dielectric layers reduces the problems of nonuniformities and the formation of pin holes in the first dielectric layer.

Abstract: A method for growing Silicon On Insulator (SOI) films using only conventional very large scale integration (VLSI) techniques is provided. By sequentially varying the flow of HCL gas during the vertical-growth, lateral-overgrowth, coalescence, and planarization stages of the epitaxial deposition process allows the formation of high-quality SOI films on wider oxide stripes suitable for general transistor applications.

Abstract: A method for trench isolation of a silicon island for device fabrication using only conventional very large scale integration (VLSI) techniques is provided. The combination of the sidewall isolation achieved with the trench isolation and the underlying oxide film create a totally dielectrically isolated structure without the possibility of latch-up between adjacent devices.

Abstract: A keyboard switch assembly is disclosed which utilizes a new switch design for providing tactile feedback to the user while nevertheless permitting long switch life. The keyboard switch assembly provides adjustable touch control to the user via a mechanical adjustment means while requiring minimal key travel. The "sandwich" arrangement of the dome and the membrane switch isolates the contacts from contamination upon activation resulting in long switch life. Furthermore, integration of all the parts in the assembly of this keyboard switch makes this keyboard more competitive and cost effective.

Abstract: A method and structure for producing a vertically built MOS structure which permits the out diffusion of dopant from a layer of chemically deposited (CVD) doped oxide into a layer of CVD laser recrystallized polysilicon is disclosed. This out diffusion is accomplished during a high temperature oxidation treatment of an intermediate structure. Source and drain mask alignment is chosen such that this out diffusion of dopant from the CVD glass at its boundary limit will meet with a diffusion of implanted ions. This process makes possible minimal overlap of the drain and source zones with the gate, thus reducing coupling capacitance while providing increased packing density.