Abstract: The systems and methods described herein include hexapod systems, Stewart platform systems and other mechanical movement systems, in which a set of independently moveable trucks support legs that couple to a working surface capable of holding a machine tool or other end-effector, and preferably wherein the trucks travel across a reference surface, such as around the circumference of a circle or along some other pre-defined geometrical pattern or track. For example, as described herein, the systems include Stewart platform machines that have six supportive legs each of which connects to a truck that can travel independently along a track. By coordinating the movement of these six trucks, the working surface can be moved in three dimensional space and can be oriented about three axes, providing control of roll, pitch and yaw.

Abstract: Power semiconductor devices having overlapping floating field plates include a primary field plate and a plurality of floating field plates which are formed on an electrically insulating region and capacitively coupled together in series between an active region of a power semiconductor device and a floating field ring. Preferably, the capacitive coupling is achieved by overlapping at least portions of the floating field plates. According to one embodiment, a power semiconductor device comprises a semiconductor substrate having a first region of first conductivity type therein extending to a face thereof and a second region of second conductivity type in the first region of first conductivity type and forming a P-N junction therewith.

Abstract: A low inductance electrical machine that may be used as an alternator or motor with low armature inductance is disclosed. Arrangements of complementary armature windings are presented in which the fluxes induced by currents in the armature windings effectively cancel leading to low magnetic energy storage within the machine. This leads to low net flux levels, low core losses, low inductance and reduced tendency toward magnetic saturation. The inclusion of additional gaps in the magnetic circuit allows for independent adjustment of air gap geometry and armature inductance. Separately excited field arrangements are disclosed that allow rotor motion to effect brush-less alternator or brush-less motor operation. An exemplary geometry includes a stator including two annular rings and a concentric field coil together with a rotor structure separated from the stator by four air gaps.

Abstract: A low inductance electrical machine which may be used as an alternator or motor with low armature inductance is disclosed. Arrangements of complementary armature windings are presented in which the fluxes induced by currents in the armature windings effectively cancel leading to low magnetic energy storage within the machine. This leads to low net flux levels, low core losses, low inductance and reduced tendency toward magnetic saturation. Separately excited field arrangements are disclosed that allow rotor motion to effect brushless alternator or brushless motor operation. An exemplary geometry includes a stator including two toroidal rings and a concentric field coil together with a rotor structure separated from the stator by four air gaps. An alternate embodiment allows for counter-rotation of two rotor elements for use as a flywheel energy storage system in which the external gyroscopic effects cancel.

Abstract: A logic level converter for translating CMOS logic signals to into differential logic signal pairs such as those associated with ECL levels. The converter includes a first converter branch coupled to the switchable CMOS level input and it provides a first switchable translated output. A second converter branch is not coupled to the input nor is it coupled to the first converter branch. The second converter branch provides a fixed reference signal output around which the output of the first converter branch switches. Changes in the input signal to the first converter branch cause its output potential to be more than or less than the potential of the fixed reference signal supplied by the second converter branch. The components of the respective branches may be tailored to position the fixed signal at a selectable level and to define the differential between the two output signals.

Abstract: A deskew circuit for synchronizing output signals from a fanout buffer. The circuit includes one capacitive element coupled to each of the buffer's output nodes. Each capacitive element is also coupled to a common floating bus. The capacitive element is preferably a capacitor and the common floating bus is electrically isolated from any power rails. The bus may be formed of polysilicon or metal.

Abstract: A fabrication- and temperature-independent power-on reset circuit for providing improved control over live insertion of integrated circuitry. The reset circuit includes a comparator having an output terminal and two input terminals, one positive and one negative. One of the two terminals is coupled to a first threshold turn-on branch and the other terminal is coupled to a second threshold turn-on branch. Both threshold branches are referenced to ground but they supply different initial potentials to the terminals of the comparator. As a result, one terminal acting as the reference terminal holds the circuit output of the present invention at a potential designed to halt circuit power-on regardless of independent enable control pin signals. The other of the two terminals does not trigger switching of the comparator output until after a common supply power rail reaches a desired potential at initial turn-on.

Abstract: A CMOS-based bus-hold circuit having overvoltage tolerance. The bus-hold circuit of the present invention includes, in addition to conventional input and latching inverters, a sense circuit and an arbiter circuit designed in combination to block overvoltage events from powering the latching inverter. The sense circuit includes a comparator designed to compare the potential of a standard high-potential power supply rail to the potential associated with a signal applied to the bus-hold circuit's input node. The higher of those two potentials is used to activate the arbiter circuit that in turn couples the higher of those two signals to a pseudo high-potential power rail. The pseudo high-potential power rail is used to supply power to the latching inverter such that the latching inverter will not be activated during overvoltage conditions, particularly when the circuit is in its high-impedance state. The bus-hold circuit may be similarly designed to establish an undervoltage tolerance as well.

Abstract: A monolayer printable polymeric film and method for making the film. The film is formed by mixing a structural material, such as polypropylene or polyethylene, with a printable material, such as vinyl-acetate or methacrylate, to form a unitary mixture prior to processing. The unitary mixture is extruded and heated so as to cause the printable material to bloom to the surface of the unitary mixture. Stretching of the mixture at temperatures greater than permissible for multi-layered films formed of separate structural and printable materials heat sets and relaxes or stress relieves the film that is formed. The result is a monolayer film that is stiffer and that lays much flatter than the prior multi-layered films that were prone to curling. The mixture is preferably heated to 270.degree. F. or greater during the stretching process.

Abstract: A modified expansion joint to provide a transition from one conduit to an adjacent conduit. The expansion joint includes a flexible coupling member and an angled transition leg having insulation on both sides thereof. The flexible coupling member takes up any variations in dimensional differences between the adjacent conduits. The transition leg provides a gradual thermal transition from a hot upstream conduit to a downstream conduit at a lower exterior surface temperature.

Abstract: A low-loss magnetic core of the claw-pole type for use in generating electrical power with a high frequency alternator is disclosed. A rotor, driven by a shaft, is made of pairs of individual poles of alternating polarity nested radially around a shaft. The rotor poles overlap each other axially and interleave circumferentially. The rotor poles are excited by a common field coil. The pairs of individual poles are made from laminated electrical steel or magnetic steel, with laminate shapes bent and bundled together to form an open three dimensional shape vaguely similar to one and one quarter turns of a spiral shape. A stator is made of ring bundles of laminated electrical steel or magnetic steel, with internal teeth. Various arrangements of windings on the stator teeth create armature poles for multiple phases of output voltage. The low loss magnetic core allows for efficient operation at high shaft speed and allows for efficient AC excitation of the rotor for special applications.

Abstract: A levitated rotor, neutrally buoyed in ultrasound transmission fluid, moves to position and aim an ultrasound transducer in up to five servo-controlled coordinates of position and tilt rotation. Stator drive/sense windings drive the rotor via a rotor magnet and sense coordinates via inductive interactions with a rotor coil. For five-axis control, one set of stator windings controls two-axis lateral translation while a second set controls axial translation plus two-axis tilt rotation. The windings produce a comparatively linear relationship between the five rotor geometric coordinates and the electromagnetic couplings that drive and sense these coordinates. To produce this linearity seamlessly over a wide coordinate range coming close to the windings, each set of windings is divided into overlapping subsets. A two-way drive/sense matrix mapping translates between up to five control coordinates and more than five winding circuits.

Abstract: A method of forming an intermediate semiconductor structure as part of a BiCMOS process to provide for improved anti-punch-through (APT) protection and improved threshold-voltage (Vt) adjustment for the MOS devices of the structure. The method includes the fabrication of a split polysilicon layer and the introduction of APT and Vt related carriers after formation of the gate oxide layer. The intermediate structure includes the gate oxide layer and a protective amorphous silicon layer formed on the surface of the gate oxide layer in an in situ process. The protective amorphous structure is formed to protect the integrity of the gate oxide layer during subsequent acid washes associated with the BiCMOS process. The amorphous layer may be deposited in a thickness substantially less than that associated with prior spilt polycrystalline silicon processes. This allows for introduction of the APT and Vt related carriers using relatively standard implanting equipment.

Abstract: A valving system for diverting fluids from one location to another. The valving system includes a valve housing and two or more dampers. The dampers are rotatably coupled to one or more shafts and are designed to move in a synchronized manner such that when opens and closes prior to the other damper or dampers doing so. The valving system of the present invention is particularly useful in the field of regenerative incineration where it is necessary to rapidly change the movement of a hazardous fluid from one regeneration bed to another. However, it may be used in any environment in which switching of the fluid flow over relatively short time periods is desired. The valving system diverts the fluid in a switchable manner that minimizes energy usage without diverting raw fluid directly to an output. A sealing system is located at the ends of the dampers.

Abstract: Power semiconductor devices having discontinuous emitter regions therein include a semiconductor substrate containing therein a collector region of second conductivity type, a buffer region of first conductivity type which forms a first P-N junction with the collector region and a drift region of first conductivity type which forms a non-rectifying junction with the buffer region. A base region of second conductivity type is also provided in the drift region and forms a second P-N junction therewith. In addition, a base contact region of second conductivity type is provided in the base region of second conductivity type. The base contact region typically has a much higher second conductivity type doping concentration therein than the base region. A preferred emitter region is also provided in the substrate. This preferred emitter region comprises an emitter contact region which is entirely surrounded in the substrate by the highly doped base contact region and a carrier emitting region.

Abstract: An ESD protection device including a transistor structure with resistive regions located within active areas thereof. The transistor structure is formed of one or more MOS transistors, preferably N-type MOS transistors. The drain regions of the transistors are modified to reduce the conductivity of those resistive regions by preventing high carrier concentration implants in one or more sections of the drain regions. This is achieved by modifying an N LDD mask and the steps related thereto, as well as a silicide exclusion mask and the steps related thereto. The modifications result in the omission of N LDD dopant from the area immediately adjacent to the underlying channel. In addition, portions of a spacer oxide remain over the drain region to be formed. Subsequent implant and siliciding steps are effectively blocked by the spacer oxide that remains, leaving a low-density drain (LDD) charge carrier concentration in those regions, except where omitted.

Abstract: An improved bicycle seat designed to prevent damage to the rider's health by transferring the riders weight from the sub scrotal area to the sit bones. The bicycle seat includes a single piece seat rail, a forward pad, a fastener for securing the forward pad to the seat rail, a combination of fasteners for securing the dual support units to the seat rail, and dual support units each having a seat platform and a seat pad.

Abstract: An accelerated endurance test structure and process that provides a wafer-level dielectric test. A wafer-level dielectric testing structure includes a heating element. The heating element may be poly-silicon or metal and is formed as a layer above a tunnel oxide layer of an integrated circuit (IC). A thermometer is provided to the heating element to regulate the temperature within the tunnel oxide area. The thermometer may be of a serpentine loop shape. Localized heating of the tunnel oxide structure occurs to a suitable temperature such as 250.degree. Celsius where the endurance test is accelerated so as to assure failure in as little as 10 seconds. Accelerated endurance data on the structure is modeled based on the Arrhenius Equation to accurately predict endurance of the devices contained on the IC.

Abstract: An output buffer for reducing the signal noise associated with the switching between logic high and logic low electrical. Signals includes a first clamping circuit linked to the pull-up output transistor of the buffer, and a second clamping circuit linked to the pull-down output transistor of the buffer. The buffer may include both clamping circuits or either the first or second clamping circuit alone, dependent upon signal shaping interests. Each of the clamping circuits includes a selectable delay stage coupled to the buffer's input, a current regulator controlled by the delay stage, and a clamping device that is coupled to the control node of the output transistor. When the current regulator is conducting, the control node of the output transistor is clamped at a potential near its threshold turn-on. As a result, when the clamping circuit is turned off, the output transistor experiences a soft turn-on, thereby reducing signal bounce and the associated noise.

Abstract: Methods of forming power semiconductor devices having insulated gate bipolar transistor cells and freewheeling diodes cells therein includes the steps of forming an array of emitter regions of second conductivity type (e.g., P-type) in a cathode layer of first conductivity type (e.g., N-type) and then forming a base region of first conductivity type on the cathode layer. An insulated gate electrode(s) pattern is then formed on a surface of the base region and used as an implant mask for forming interleaved arrays of collector and anode regions of second conductivity type in the base region. An array of source regions of first conductivity type is then formed in the collector regions, but not the anode regions, by implanting/diffusing source region dopants into the collector regions. To achieve preferred device characteristics, the array of collector regions is formed to be diametrically opposite the array of emitter regions to thereby define a plurality of vertical IGBT cells.