Abstract: An LED driver circuit and method are disclosed where a plurality of arrays of light emitting diodes each have a transistor connected to each respective array of light emitting diodes. A PWM controller has an input for receiving a voltage reference and an output connected to selected transistors for driving the selected transistors and setting a PWM duty cycle for the selected arrays of light emitting diodes to determine the brightness of selected light emitting diodes. An oscillator is connected to the PWM controller for driving the PWM controller.

Abstract: A sense amplifier circuit for a memory cell includes a sense amplifier that is operable to be coupled to a memory cell via data lines, and including read bus complement and read bus true lines operative with a data output through which a data output signal is passed. An equalization circuit and enable circuit are operable with the sense amplifier. A control circuit is operable for disconnecting the data output from preferably the one of the read bus complement line and minimize unwanted transitions on the data output signal.

Abstract: A microprocessor and associated method includes a plurality of resources for executing instructions, and an out-of-order instruction shelf for priority/age tracking of the instructions. The instruction shelf has an instruction pool with a plurality of slots therein for storing respective instructions, and an instruction age tracker for storing therein a matrix of rows and columns of logic states associated with relative ages of instructions. The logic states in a given column and row of the matrix are associated with a respective slot of the instruction pool. Also, the microprocessor includes an instructions scheduler for performing at least one logic function on each column of the matrix to determine an oldest instruction, for dispatching instructions to the plurality of resources based thereon, and for updating the matrix based upon dispatched instructions.

Abstract: An integrated circuit for a smart card may include a universal serial bus (USB) transceiver and a microprocessor connected to the USB transceiver and operable in a test mode and a user mode. The microprocessor, when in the test mode, upon receiving at least one test request from the USB host device may cause the USB transceiver to output test data, read back the test data from the USB transceiver, compare the test data with the test data read back from USB transceiver, and generate test results for the USB host device based upon the comparison.

Abstract: A smart card includes a card body and integrated circuit carried by the card body, including a microprocessor operative for communicating with a host and driving a signaling device indicative of smart card transactions between the smart card and a USB port of the host. The microprocessor is operative for modulating the signaling device based on operational attributes of the smart card and/or transactions between the smart card and USB port of the host.

Abstract: A smart card includes a card body and integrated circuit carried by the card body. A microprocessor communicates with a host when the smart card is inserted within a smart card reader. The integrated circuit is operative for driving at least one multi-color light emitting diode (LED) indicative of smart card transactions between the smart card and a USB port of the host and operative for modulating the multi-color LED based on operational attributes of the smart card and/or transactions between the smart card and USB port of the host.

Abstract: An integrated circuit and method are provided for sensing activity such as acceleration in a predetermined direction of movement. The integrated released beam sensor preferably includes a switch detecting circuit region and a sensor switching region connected to and positioned adjacent the switch detecting circuit region. The sensor switching region preferably includes a plurality of floating contacts positioned adjacent and lengthwise extending outwardly from said switch detecting circuit region for defining a plurality of released beams so that each of said plurality of released beams displaces in a predetermined direction responsive to acceleration. The plurality of released beams preferably includes at least two released beams lengthwise extending outwardly from the switch detecting circuit region to different predetermined lengths and at least two released beams lengthwise extending outwardly from the switch detecting circuit region to substantially the same predetermined lengths.

Abstract: A temperature compensated clock and method of clocking systems are provided. The clock preferably has an oscillator for generating an oscillating waveform signal at a preselected frequency and a frequency divider responsive to the oscillator for dividing the frequency of the oscillating waveform signal. A temperature monitoring circuit is positioned responsive to a voltage input signal independent of temperature and a voltage input signal proportional to temperature for monitoring temperature variations. A temperature compensating circuit, preferably including a programmable scaling circuit, is responsive to the frequency divider and the temperature monitoring circuit for scaling the divided frequency of the generated waveform and thereby advantageously produces a temperature compensated output timing signal.

Abstract: A method, apparatus and network device for controlling the flow of network data arranged in frames and minimizing congestion, such as in the receive port of an HDLC controller is disclosed. A status error indicator is generated within a receive FIFO memory indicative of a frame overflow within the receive FIFO memory. In response to the status error indicator, an early congestion interrupt is generated to a host processor indicative that a frame overflow has occurred within the receive FIFO memory. The incoming frame is discarded and the services of received frames are enhanced by one of either increasing the number of words of a direct memory access (DMA) unit burst size, or modifying the time-slice of other active processes.

Abstract: A method and network device are disclosed using a look-ahead watermark in a FIFO memory. In accordance with the present invention, a watermark interrupt is generated from a FIFO memory when data in the FIFO memory has crossed a watermark threshold. A data burst is transferred through a direct memory access unit to the FIFO memory. A look-ahead watermark flag is checked at the FIFO memory to determine if sufficient memory space exists inside the FIFO memory for an additional data burst, which is transferred through the direct memory access unit to the FIFO memory when the look-ahead watermark flag indicates that sufficient memory space is available.

Abstract: A system and method for reducing transfer latencies in fencepost buffering requires that a cache is provided between a host and a network controller having shared memory. The cache is divided into a dual cache having a top cache and a bottom cache. A first and second descriptor address location are fetched from shared memory. The two descriptors are discriminated from one another in that the first descriptor address location is a location of an active descriptor and the second descriptor address location is a location of a reserve/lookahead descriptor. The active descriptor is copied to the top cache. A command is issued to DMA for transfer of the active descriptor. The second descriptor address location is then copied into the first descriptor address. The next descriptor address location from external memory is then fetched and placed in the second descriptor address location.

Abstract: A ballast circuit and method for operating a lamp includes a lamp preheat/ignition circuit for preheating and igniting the lamp. A ballast controller integrated circuit is operatively connected to the preheat/ignition circuit wherein the lamp preheat/ignition circuit is operatively controlled in a a) preheating mode wherein the lamp is preheated at a preheating frequency for a predetermined period of time; b) a user programmable intermediate ignition mode wherein the lamp is heated at an intermediate ignition frequency that is lower than the preheating frequency; and c) an operating mode wherein the lamp is operated at a final operating frequency that is lower than the intermediate ignition frequency.

Abstract: The probe card of the present invention permits testing of a semiconductor device-under-test under high temperatures and includes a plurality of printed circuit boards stacked together to form a probe interface board having a top surface and a lower testing face. A heat sink is mounted on the probe interface board at the top surface and extends to the lower testing face. A needle supporting module is carried by the heat sink at the lower testing face and has a plurality of probe needles for electrically connecting to electrical contacts of a semiconductor device-under-test.

Abstract: A thermal ink jet printhead system has a printhead with base member and a plurality of ink flow channels formed in the base member that connect to an ink reservoir and terminate in a nozzle through which ink is expelled. A heating element is associated with each ink flow channel. A monolithically integrated multiple output power driver circuit is formed as a semiconductor integrated circuit and connected to each heating element in the printhead. The multiple output driver circuit includes a power MOS transistor connected to each heating element. A reference circuit is operatively connected to each gate of the power MOS transistor and includes a reference transistor having a gate and a reference amplifier that receives as inputs a reference voltage and a source of current. An amplifier output is operatively connected to the gates of the power output transistors and the gate of the reference transistor.

Abstract: A method and device of creating one or more buffer structures in a shared memory that exists between a host and a network device is disclosed. The method includes the step of storing within a block of shared memory an administration block having a base address and a descriptor ring parameter, which includes information relating to a descriptor ring and frame data buffer sizes. The base address of the administration block is written into the network device. An initialization command is then issued from the host to the network device. The network device reads the administration block and shared memory and one or more descriptors are constructed within the network device. Each descriptor points to a frame data buffer within shared memory. The descriptors are then stored.

Abstract: A ballast compatible with different types of gas discharge lamps includes a power supply and a controller connected to the power supply. The controller includes a memory having a plurality of desired operating parameters stored therein for respective different types of gas discharge lamps. A sensing circuit causes the power supply to supply a current to the gas discharge lamp prior to start-up and senses a voltage based thereon indicative of a type of the gas discharge lamp. A control circuit causes the power supply to provide the desired operating parameters based upon the type of gas discharge lamp. Since the desired operating parameters are applied to the gas discharge lamp, the life of the lamp is increased.

Abstract: A non-sampling cascaded current mode analog-to-digital converter is formed of cascaded threshold detector bit cells driven by a transconductance amplifier for substantially instantaneously propagated current mode operation. A front end stage receives an input voltage representative of the quantity to be digitized, and outputs a pair of currents to N−1 cascaded, identically configured threshold comparator-based bit cells, N being the number of bits of resolution of the converter. A bit cell resolves a digital bit and couples a pair of output currents to the next bit cell. The N−1th bit cell in the cascaded architecture is configured to provide both the next to least significant bit and the least significant bit.

Abstract: A method and apparatus for reducing convergence time in a digital filter. When the digital filter is initially run, the coefficients in the digital filter are adjusted to reduce error in the output of the digital filter. When the adjusted coefficients meet a selected error level, these coefficients are stored in a memory and the digital filter filters data. The next time the digital filter is run, the stored coefficients are loaded into the digital filter and a number of iterations are run in which the coefficients are adjusted. Then, a determination is made as to whether the error level meets a threshold that may be the same as the selected error level. If the coefficients meet the threshold, the coefficients are stored in the memory and the filter is then used to filter data.

Abstract: A first-in first-out (FIFO) memory device includes a plurality of memory locations having sequential binary addresses, a write address pointer for sequentially accessing the memory locations to write data therein, and a read address pointer for sequentially accessing the memory locations for reading data therefrom. The method and apparatus add an inverted write binary address of the write address pointer to a read binary address of the read address pointer, add one, and discard the most significant bit (MSB) to define the number of empty memory locations.

Abstract: A voltage regulator includes a power transistor receiving a drive current, and a current limit protection circuit connected to the power transistor. The current limit protection circuit includes a first resistance connected to the power transistor for sensing an output current, a limit switch transistor connected to the power transistor and to the first resistance, and a current generator and second resistance connected thereto. The current generator and second resistance biases the limit switch transistor to divert drive current from the power transistor based upon the output current through the first resistance exceeding a threshold. The first resistance has a value less than a value of the second resistance. The first resistance can be made considerably smaller than otherwise to thereby reduce power consumption.