Abstract: A method for timing and noise analysis in designing data processing chips is provided. The process begins by wiring all unconnected nets in the design and then using a 2½ D capacitance extraction technique built into a detailed router to extract all of the wired nets. The data from the extracted nets is then process using a timing and analysis tool. Optimization programs are then used to generate fixes for any nets in the design which contribute to timing and noise failures. The present invention gives designers the capability of fast and accurate interconnect extraction within the routing tool. In addition, this technique is incremental. Any wiring changes can be quickly re-extracted, since only local information is required for extraction. This incremental capability allows designers to perform quick iterations of wiring, extraction and timing analysis.