Abstract: An isolation technique is provided for improving the overall planarity of isolation regions relative to adjacent active area silicon mesas. The isolation process results in a trench formed in field regions immediately adjacent the active regions. The trench, however, does not extend entirely across the field region. By preventing large area trenches, substantial dielectric fill material and the problems of subsequent planarization of that fill material is avoided. Accordingly, the present isolation technique does not require conventional fill dielectric normally associated with a shallow trench process. While it achieves the advantages of forming silicon mesas, the present process avoids having to rework dielectric surfaces in large area field regions using conventional sacrificial etchback, block masking and chemical-mechanical polishing. The improved isolation technique hereof utilizes trenches of minimal width etched into the silicon substrate at the periphery of field regions, leaving a field mesa.

Abstract: A computer system which includes an electromagnetic hoodlock, and does not have any simple way to bypass the hood-lock The hoodlock consists of a spring-loaded solenoid, and is controlled by the system microprocessor. The system chassis may only be opened by a user with sufficient rights, after entering a password, or after an administrative command is sent over the computer network.

Abstract: A circuit and method for reducing voltage oscillations at the output leads of a digital integrated circuit. A circuit for reducing voltage oscillations on the output leads of a digital integrated circuit comprising a positive voltage charge pump unit coupled to an output driver, a negative voltage charge pump unit also coupled to the output driver and a sense and control unit coupled to both the negative voltage charge pump unit and the positive voltage charge pump unit is presented. The sense and control unit is configured to determine whether switching current is present in the source or drain of the output driver. If switching current is present in the source, then the sense and control unit is further configured to connect the positive voltage charge pump unit to the source. If switching current is present in the drain, then the sense and control unit is still further configured to connect the negative voltage charge pump unit to the drain.

Abstract: The bits of a data block are assigned to a plurality of logical groups such that at most one bit corresponding to a component is assigned to a logical group. This assignment ensures that a component failure may introduce at most one bit error to a logical group. Each logical group uses a single error correcting code to detect and correct bit errors. A parity bit is appended to a data block that includes a plurality of logical groups. The parity bit may be used in conjunction with the single error correcting codes to determine whether a detected error is a single bit error or a multiple bit error. If the detected error is a single bit error, the error correction codes may be used to correct the error. If the detected error is a multiple bit error, an uncorrectable error may be reported.

Abstract: In a first aspect of the invention, branch prediction hardware, comprising logic and interconnect, is configurable via a control line to alter the manner in which the branch prediction is generated. The configuration can be done programmatically in software. Or, the configuration can be done by hardware in response to processor events. Such processor events include the loading of the CS register and changes in the instruction workload. In a second aspect of the invention, related to speculative execution, the directions of a plurality of branches are predicted based partly on resolved branch history information. Tentative branch history information is then stored for each of the predicted branches. When a predicted branch is resolved, the resolved branch history information is updated based on the stored tentative branch history information for the branch most recently resolved. Additionally, the predictions may be partly based on preceding unresolved branch predictions if any are outstanding.

Abstract: A method and apparatus for detecting floating transistor gates within a netlist model of an integrated circuit is disclosed. All transistor gates and input nodes coupled to the transistor gates are identified. These input nodes are then used to generate a resistor card. The resistor card is used in conjunction with the original netlist during simulation to couple two resistors to each input node. The first resistor is coupled between the input node and a high potential, and the second resistor is coupled between the input node and a lower potential. The resistors may be configured to have equal resistance values. The resistance values may be large enough to ensure that the current conducted through the resistors will be minimal in relation to the currents in the circuit when the input node is not floating. The resistance values may be small enough to overcome any leakage currents present in the circuit.

Abstract: A memory circuit which enables storage of three logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by the state of a tri-state flip-flop. By enabling the current to be detected as positive, negative, or zero, it becomes possible to represent more than one bit of information with the state of the flip-flop.

Abstract: An apparatus for performing speculative stores is provided. The apparatus reads the original data from a cache line being updated by a speculative store, storing the original data in a restore buffer. The speculative store data is then stored into the affected cache line. Should the speculative store later be canceled, the original data may be read from the restore buffer and stored into the affected cache line. The cache line is thereby returned to a pre-store state. In one embodiment, the cache is configured into banks. The data read and restored comprises the data from one of the banks which comprise the affected cache line. Instead of forwarding store data to subsequent load memory accesses, the store is speculatively performed to the data cache and the loads may subsequently access the data cache. Dependency checking between loads and stores prior to the speculative performance of the store may stall the load memory access until the corresponding store memory access has been performed.

Abstract: There is provided a novel powered loudspeaker implemented to be compatible with the USB specification. The powered speaker includes a speaker driven by a power amplifier coupled to a power supply. Both the amplifier and the power supply, in turn, are coupled to a USB controller. The controller is configured to provide USB functionality and compatibility. In addition, provides a phase locked loop (PLL) for recovering a timer clock from the received data stream. The present invention further includes a function whereby the absence of data on the relevant channel is detected and the output to the speakers is muted in response thereto. A further circuit is provided that controls when the output to the speaker is turned on such that no clicks or pops occur at power-up or when the device or bus is not stable. In addition, tone control, including base and treble filters, volume control, and balance between left and right outputs (in a stereo version) are provided.

Abstract: A memory circuit which enables storage of more than two logic states in a memory cell. Since the additional logic states may be used to represent additional information bits, this memory circuit increases the number of bits that may be stored per memory cell, thereby increasing the storage density and reducing the cost per bit. The disclosed memory circuit comprises an analog-to-digital converter coupled to detect a current through a transistor in a memory cell. The current is determined by a charge stored on the transistor's gate. By enabling the current to be detected in discrete increments, it becomes possible to represent more than one bit of information with the charge stored in the memory cell. Usage of additional increments necessitates more precise storage and detection circuitry. In one embodiment, the storage circuitry uses feedback to obtain a greater logic state retrieval accuracy.

Abstract: A method and apparatus for encrypting and decrypting a microprocessor serial number. First and second encryption keys and a serial number are provided in microprocessor machine specific registers. The serial number is encrypted using the first key. The encrypted serial number is encrypted using the second key. The first encryption key may be encrypted along with the serial number using the second key. The double encrypted serial number is then stored in memory provided for that purpose.

Abstract: A reorder buffer including a speculative storage section and a retired storage section is provided. The speculative storage section stores speculative register states; while the retired storage section stores committed register states corresponding to the execution of instructions which have been retired. The dependency checking logic of the reorder buffer checks dependencies for operands of instructions being dispatched against both the speculative and retired storage sections. In this manner, a dependency is always detected within the reorder buffer. Therefore, no selection between a register file value and a value provided from the reorder buffer need be made. In fact, the register file may be eliminated from a microprocessor employing the reorder buffer. The retired storage section comprises a shiftable queue in one embodiment. The shiftable queue stores committed register states and indications of the architected registers corresponding to the committed register states.