Abstract: A deformable cap for a computer pointing device is provided that may be particularly useful for miniature joystick-type pointing devices such as the TrackPoin™ and ScrollPoint™ devices manufactured by the IBM corporation of Armonk, N.Y. When an operator places a fingertip on the cap, the cap deforms thereby advantageously increasing the surface area of contact between the cap and the fingertip. All embodiments of the cap are placed on an upper portion of a control stick of the pointing device. A first embodiment of the cap includes a bottom support, a disc, a plurality of wire supports, and an elastic cover that overlays the disc and wire supports. An inner surface of the cover may be scored to ensure repeatable deformation of the cap. A spring may be attached to a lower surface of the disc to assist the cap in regaining its original shape once the operator's fingertip is removed.

Abstract: Disclosed herein are techniques by which a Layer-2 entity determines whether a mobile terminal requesting association or reassociation therewith determines whether the requesting mobile terminal shall continue using its current IP address or whether it requires a new IP address. The Layer-2 entity makes this determination based upon an examination of the contents of the association or reassociation request message received thereby. Contained in the association or reassociation reply message returned by the Layer-2 entity shall either be an instruction, to the mobile terminal, to continue using its current IP address or a new IP address to be used, by the mobile terminal in place of its current IP address.

Abstract: A high volume lens curing system is described. The high volume lens curing system may be configured to cure multiple eyeglass lenses in a continuous manner. An embodiment of a system may include a mold assembly, a lens curing apparatus, a mold filling apparatus and a controller. In some embodiments, the system may include a conveyor system and/or a coating apparatus.

Abstract: A system and method are presented for the encapsulation of a protocol stack in a voice telephony processor. Utilizing the system and method disclosed herein, digital voice telephony signals received in TDM frame-based format are converted to packet-based or cell-based format for transmission on a network, and vice-versa. The system and method may be embodied as a functional block within a specialized high-density integrated circuit voice processor. The voice processor employs on-chip digital signal processors (DSPs) to perform echo cancellation, dynamic range compression/expansion, and other processing on voice data. Advantageously, the encapsulation process of the disclosed herein does not impact the throughput of the DSPs. Instead, voice data is reformatted and prefixed with a header for the appropriate protocol layers using a dedicated on-chip packet control processor and linked list data structures managed by indexed direct memory access (DMA) controllers.

Abstract: A memory controller provides fast processing of sequential split memory access instructions which include a split write instruction. In a split write instruction, a write address and write request are provided to the memory controller in an initial transaction while write data can be provided to the memory controller in a later transaction. The memory controller includes a sideline buffer, for buffering incomplete write instructions, and memory control logic which ensures proper execution of the sequential memory access instructions. Upon receiving an incomplete write instruction, the memory control logic stores the corresponding write request and write address in the sideline buffer until corresponding write data becomes available. The memory control logic determines if there is overlap between memory space to be occupied by an initial write data block and memory space to be occupied by a subsequent read data block or second write data block, of a read or write instruction respectively.

Abstract: An unequal error protection Reed-Muller code and method for designing a generator matrix and decoder. A conventional RM code is concatenated with the combination of itself and a subcode of itself. The new generator matrix is decomposed to include empty submatrices. The resulting generator matrix allows parallel decoding of separate portions of the received code word vectors.

Abstract: An application specific integrated circuit, ASIC, having an advanced high-speed bus, AHB, operating in Advanced Microcontroller Bus Architecture, AMBA, and a bridge for connecting to an off-chip device is disclosed. The bridge includes a logical section and a buffer section for modifying AMBA signals to accommodate the differing clock speeds, voltages and signals required by the off-chip device. The logic section includes clock division and registers to store variables identifying the off-chip device and data being transferred from the AHB to the off-chip device. The buffer section provides any conversion of signal voltage levels between the core ASIC voltages and the input/output voltages required by the off-chip device.

Abstract: An efficient and reliable technique is disclosed for detecting faults which occur in FIFO's, including control faults which are specific to FIFO's, as well as faults common to conventional memories, such as interport faults and faults that occur in single port memories. The technique utilizes a sequence of read, write and control operations, thereby avoiding the need to directly observe internal values within the FIFO, such as the full and empty flag values and the shift register values.

Abstract: A computer system includes a real-time interrupt that causes the operating system to determine which isochronous tasks are pending. In one embodiment, applications that include isochronous tasks are certified to be well-behaved and the operating system will only initiate applications that are known to be well-behaved by checking a list of certified applications. The operating system will not initiate an application if insufficient resources are available for executing the tasks of the application. Each application informs the operating system of an execution rate and a maximum duration of its isochronous tasks. Prior to initiating an application, the operating system verifies that resources are available to execute the isochronous tasks of the application. The operating system includes a non-maskable interrupt to terminate isochronous tasks. Termination may be necessary if an isochronous task fails to execute within its specified maximum duration.

Abstract: A “Wrapper” system and method are presented for integrating built-in self-test (BIST) and built-in self-repair (BISR) functions in a semiconductor memory device. The wrapper reduces the usual dependency of BISR circuitry on the BIST design, so that modifications and enhancements to the BIST may be made without requiring significant changes to the BISR. A generic BIST engine with an extended address range (spanning both the accessible and the redundant rows) is used to test the entirety of memory as a single array, preferably using a checkerboard bit pattern. The memory is tested in two stages, using the same BIST algorithm. In the first stage, faulty rows in each memory portion are identified and their addresses recorded. At the end of the first stage a repair process allocates good redundant rows to replace faulty accessible rows. During the second stage, repair of the accessible memory portion is verified, while defects among the redundant portion are ignored.

Abstract: A bridge for connecting a DSP to an ASIC on-chip bus as a master on the bus. The bridge includes a DSP instruction unit master interface and a DSP data unit master interface to convert DSP instruction unit and data unit external signals into bus protocol signals. An arbiter is provided to receive the signals from the two DSP interfaces and selectively pass the signals to a generic bus master which couples the signals to the on-chip bus. A synchronization unit is provided to insure alignment of positive clock transitions between the different clock frequencies of the ASIC and the DSP and to buffer signals as needed. The generic bus master couples signals from the arbiter and the synchronization unit to the ASIC bus in full compliance with the bus protocol.

Abstract: An integrated circuit structure and a method for packaging an integrated circuit are described. The integrated structure includes an integrated circuit that is inverted and solder bump mounted to a substrate. An underfill is used to encapsulate the solder bumps and form a rigid support layer between the integrated circuit and the substrate. A heatspreader, which has larger planar dimensions than the integrated circuit, is centrally attached to an upper surface of the integrated circuit with a thermally conductive material. Lateral portions of the heatspreader extending beyond the edges of the integrated circuit are attached to the substrate and sides of the integrated circuit by a thermally conductive underfill material. The thermally conductive underfill material thus employed, among other things, provides a robust mechanical support to the heatspreader and integrated circuit structure and eliminates the need for additional support structures such as conventional stiffener rings.

Abstract: An inexpensive synchronous detection module is disclosed for a sideband signal receiver that provides for flexibility in design of the tuner. The detection module is adaptable to detection of upper or lower sideband signals. One embodiment includes an analog-to-digital converter, a Hilbert transform filter, a sideband selection switch, a complex multiplier, a carrier recovery. loop, a matched filter, and a decimator. The analog-to-digital converter oversamples an intermediate frequency (IF) signal from the tuner, and the Hilbert transform filter generates a Hilbert transform of the digital IF signal. An analytic IF signal can be generated from the digital IF signal by multiplying the Hilbert transform of the digital IF signal by j(=sqrt(−1)), and adding the resulting imaginary-valued signal to the digital IF signal. The sideband selection switch can “flip” the analytic IF signal by inverting the imaginary-valued signal.

Abstract: A system and method are presented for using spare gates to repair logic errors in a digital logic IC with a hierarchical physical design. According to the system and method, the spare gates are organized as scalable modules, consisting of varying numbers of identical sub-modules. The scalable modules are not part of the functional circuitry of the IC, but the spare gates within their sub-modules may be incorporated into faulty functional circuitry to correct the logic error. This is accomplished by altering the metalization layer of the IC to reconnect the spare gates, and does not require changing the physical layout (i.e., adding more pins, relocating gates, etc.) of the IC.

Abstract: A self-time circuit and method are presented for reducing the write cycle time in a semiconductor memory. A “dummy” memory cell having the same timing requirements as the functional cells, and associated write logic are added to the standard circuitry of the memory device. The dummy write cell receives the same control signals used to write data to the functional cells of the memory, and is configured to issue a completion signal when a write access is concluded, causing the write cycle to be terminated. The circuit and method permits write cycle time to be reduced to the lowest practical value, independently of the read cycle time. This potentially increases the overall operating speed of the memory device. The circuit and method disclosed herein are adaptable to the most common types of memory devices, such as SRAM, DRAM and CAM.

Abstract: A method is presented for self-test and self-repair of a semiconductor memory device. Prior to the self-repair stage, both redundant and regular memory portions are comprehensively tested, preferably using a checkerboard bit pattern. Faulty rows identified in each memory portion during testing are recorded. Known-bad rows in regular memory are then replaced by known-good redundant rows in the self-repair stage, and the resulting repaired memory is retested for verification. Compared to existing methods, the new method is believed to provide improved test coverage, making it both more effective in identifying non-repairable memory devices and less prone to fail repairable ones.

Abstract: An apparatus and method for translating variable-length instructions to fixed-length instructions. The apparatus includes instruction decompression logic and caching logic. The instruction decompression logic receives a first portion of an instruction data block, an output signal produced by the caching logic, and a control signal during a time period. The instruction decompression logic produces a fixed-length instruction during the time period dependent upon the first portion of the instruction data block, the output signal produced by the caching logic, and the control signal. The caching logic includes a storage unit. During the time period, the caching logic receives a second portion of the instruction data block and the control signal. The caching logic stores the second portion of the instruction data block within the storage unit during the time period dependent upon the control signal.

Abstract: A structure for programming a memory cell on an integrated circuit provides access at multiple mask levels of the integrated circuit to each of the programming voltages which may be used to program the memory cell. In an embodiment, the structure includes a conductive signal path extending through multiple horizontally conductive layers of the integrated circuit from a programming voltage pad (or node) to an input of the memory cell. The conductive signal path includes portions selected from multiple alternate path portions formed within the multiple horizontally conductive layers through which the signal path extends. An embodiment of a method for making a mask includes selecting one of multiple configurations of the programming structure portion to be formed using the mask. A computer-usable carrier medium may include digital representations of the alternative configurations for a programming structure portion from which a programming structure pattern may be selected.

Abstract: A method and a means for determining an IDDQ test limit of an integrated circuit are provided. In particular, a method is provided which includes measuring the IDDQ value of a test structure formed upon a die derived from the same lot of wafers as an integrated circuit. The method may further include setting the IDDQ test limit based upon the measured IDDQ value. In some embodiments, setting the IDDQ test limit may include correlating the IDDQ value of the test structure to calibration data. Accordingly, a means for conducting such a method may include one or more test structures formed upon a die and calibration data adapted to correlate a test structure IDDQ value to an IDDQ test limit of an integrated circuit. In some cases, the means for determining the IDDQ test limit may further include a means for increasing a substrate leakage current of the test structure.

Abstract: A digital communications system employing modulated Walsh functions to convey data across a communications channel. In one embodiment, the system includes a transmitter having a constellation encoder, and a Walsh constellation modulator. The constellation encoder receives a sequence of data words and converts it into a sequence of constellation signal point labels. The modulator receives the sequence of labels, and responsively generates one or more amplitude-modulated Walsh functions which are summed to produce a modulated signal. The modulated signal passes through a communications channel to a receiver. The receiver includes an analog-to-digital converter (ADC) and a demodulation circuit. The ADC oversamples the received signal. The demodulation circuit manipulates the sign of the samples to effectively multiply the received samples with one or more Walsh functions, and sums the resulting values over one symbol interval to determine the modulated amplitude of the corresponding functions.