Abstract: Briefly, in accordance with an embodiment of the invention, a method and apparatus to write back data is provided. The method may include setting a status corresponding to a block of data in response to a change in address mapping to indicate that the block of data is pending write back. The apparatus may include a storage area to store a status associated with a block of data to indicate that the block of data is pending write back and is not accessible with the current address mapping. Other embodiments are described and claimed.

Abstract: An apparatus to use a refrigerator in a mobile computing device is described. In one embodiment, the refrigerator includes a cold reservoir to absorb heat generated by a heat generating unit of the mobile device. A heat exchanger is used to dissipate heat of a hot reservoir of the refrigerator. In an alternative embodiment, the apparatus includes a working fluid loop, with a fluid of the loop to be in thermal contact with the heat generating device, and the cold reservoir of the refrigerator to absorb heat from the fluid.

Abstract: The effects of a self-erase phenomenon when accessing imprinted ferroelectric memory cells that have non-conductive electrode interfaces that reduce remnant polarization and decrease signal margin are eliminated. A self-erase control pulse asserted after an access pulse is utilized. The self-erase control pulse has a magnitude sufficient to offset a remnant charge on the non-conductive electrode interfaces after the removal of the access pulse.

Abstract: A method, system, and apparatus for high data rate parallel plate mode signaling.

Abstract: A Bluetooth based security system utilized to provide ad-hoc security services to secured assets. Such a Bluetooth based security system comprises a secured device (SD) equipped with Bluetooth (BT) technology; a plurality of Bluetooth Access Points (BTAPs) located at designated points to establish a BT link with the secured device (SD); and a security server (SS) connected to all BTAPs and arranged to provide access control and security services for the secured device (SD), wherein the security server (SS) obtains attribute information of the secured device (SD), including an unique device identification (ID) and a last known location of the secured device (SD), activates a lock with the secured device (SD), and sends location information of a designated BTAP and an unlock code to the secured device (SD), via the designated BTAP.

Abstract: An apparatus to use a refrigerator in a mobile computing device is described. In one embodiment, the refrigerator is a thermoacoustic based refrigerator. In one embodiment, the refrigerator is a Stirling based refrigerator.

Abstract: A method of storing data related to system initialization in a data hub in a manner which provides accessibility to the data in either the pre-boot environment or the run-time environment.

Abstract: Briefly, one or more memory access parameters used to access a memory cell are adjusted based on a sensed operating temperature. In one embodiment, a pulse width of an access voltage is increased as the operating temperature decreases below a threshold. In another embodiment, a drive voltage is decreased as the operating temperature increases.

Abstract: A power management technique uses system management interrupt (SMI) to manage performance states of logical processors in a physical processor. Each logical processor is associated with a virtual performance state and an actual performance state. A request to retrieve or to change the virtual performance state causes the SMI to be generated. The virtual performance state is a state known to an operating system (OS). The actual performance state is a state that the logical processor is operating at.

Abstract: Briefly, voltages to write a memory cell are adjusted if the memory cell is determined to be imprinted. In one embodiment, a positive voltage not including zero is applied to one of a bit line and a word line and a negative voltage not including zero is applied to another of the bit line and the word line to write a specified logic state to an imprinted memory cell. Neighboring cells do not receive disturb voltages in excess of a disturb voltage threshold.

Abstract: A method, circuit, and system for providing a power good signal for a voltage regulator are described. The voltages of the two input pins to an error amplifier within a voltage regulator may be compared to determine if the error amplifier is operating in the linear range. If it is determined the error amp is operating in the linear range, then the voltage regulator is operating properly, and the power good signal may be set to a high level.

Abstract: An apparatus comprising: a die having a top metal layer, the top metal layer comprised of at least a first metal line and a second metal line; a passivation layer covering the top metal layer; a C4 bump on the passivation layer; and a first passivation opening and a second passivation opening in the passivation layer, the first passivation opening to connect the first metal line to the C4 bump, and the second passivation opening to connect the second metal line to the C4 bump.

Abstract: An apparatus comprising: a die having a top metal layer, the top metal layer comprised of at least a first metal line and a second metal line; a passivation layer covering the top metal layer; a C4 bump on the passivation layer; and a first passivation opening and a second passivation opening in the passivation layer, the first passivation opening to connect the first metal line to the C4 bump, and the second passivation opening to connect the second metal line to the C4 bump.

Abstract: The present invention is a CMOS SRAM cell comprising two access devices, each access device comprised of a tri-gate transistor having a single fin; two pull-up devices, each pull-up device comprised of a tri-gate transistor having a single fin; and two pull-down devices, each pull-down device comprised of a tri-gate transistor having multiple fins. A method for manufacturing the CMOS SRAM cell, including the dual fin tri-gate transistor is also provided.

Abstract: A method for generating a unique device ID for each addressable device in a stack of multiple addressable devices by encoding a device ID for one device in the stack and determining a device ID for each of the other devices based on the device ID of an adjacent device in the stack.

Abstract: A low dielectric constant material having a first fluorine concentration in a near-surface portion and a second fluorine concentration in an interior portion provides an insulator suitable for use in integrated circuits. In a further aspect of the present invention, fluorine is depleted from a near-surface portion of a fluorine containing dielectric material by a reducing plasma. Fluorine in fluorinated low-k dielectric materials, such as SiOF, amorphous fluorinated carbon (a-F:C) and parylene-AF4, can react with surrounding materials such as metals and Si3N4, causing blisters and delamination. Treatment of these fluorinated low-k dielectric materials in a reducing plasma, which may be produced from precursor gases such as H2 or NH3, depletes the surface region of fluorine and hence reduces reaction with surrounding materials and F outgassing. By selecting an appropriate point in the integration flow, specific interfaces which are most susceptible to F-attack can be targeted for depletion.

Abstract: A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.

Abstract: A porous medium, such as a low dielectric constant film, can be made into an aggregate material to provide increased mechanical strength on a temporary basis. This can be achieved by, for example, a permeable modification treatment of the porous medium. By introduction of a secondary component into the void fraction of the porous medium, the mechanical properties are temporarily improved such that a porous film has mechanical characteristics similar to those of a much stiffer film. Methods in accordance with the present invention permit effective processing of highly porous interlayer dielectric (ILD) materials in a Cu damascene interconnect technology. Once a process operation such as a Cu chemical mechanical polishing (CMP) process, which requires greater mechanical strength than that provided by the porous film alone, is completed, the secondary component can be removed by methods such as displacement or dissolution.

Abstract: The present provides a method for forming a porous metal silicate dielectric layer having a dielectric constant of less than 2.0. The porous metal silicate dielectric formed by embodiments of the present invention is suitable for integration into the microelectric device manufacturing process. By carefully controlling the amount and type of surfactant used, the pore size and structure of the dielectric layer can be predetermined.

Abstract: A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.