Patents Represented by Attorney Cyndi Wheeler
  • Patent number: 7191281
    Abstract: A mobile computer system such as mobile PC operable between a normal, stationary mode and a Navigation mode for optimal system performance and power management for mobile applications.
    Type: Grant
    Filed: June 13, 2001
    Date of Patent: March 13, 2007
    Assignee: Intel Corporation
    Inventor: Sundeep M. Bajikar
  • Patent number: 7187066
    Abstract: Methods and systems for attaching a chip to a next level package by directing radiant energy at the chip back side while substantially preventing irradiation of the next level package are described.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: March 6, 2007
    Assignee: Intel Corporation
    Inventor: Kristopher J. Frutschy
  • Patent number: 7186614
    Abstract: A method of forming high performance logic transistors and high density flash transistors on a single substrate is disclosed. In one embodiment, the method comprises: forming a logic gate stack in a logic region on a substrate, forming a flash memory gate stack in a flash region on the substrate, depositing a hardmask layer over the logic gate stack and over the flash memory gate stack, patterning the hardmask in the logic region so that areas of hardmask remain where logic gates are desired, patterning the flash gate stack in the flash region to form flash memory gates, and etching the logic gate stack using the remaining hardmask as a mask to form logic gates.
    Type: Grant
    Filed: November 10, 2003
    Date of Patent: March 6, 2007
    Assignee: Intel Corporation
    Inventors: Henry S. Chao, Ervin T. Hill
  • Patent number: 7183597
    Abstract: The present invention relates to a method of forming a quantum wire gate device. The method includes patterning a first oxide upon a substrate. Preferably the first oxide pattern is precisely and uniformly spaced to maximize quantum wire numbers per unit area. The method continues by forming a first nitride spacer mask upon the first oxide and by forming a first oxide spacer mask upon the first nitride spacer mask. Thereafter, the method continues by forming a second nitride spacer mask upon the first oxide spacer mask and by forming a plurality of channels in the substrate that are aligned to the second nitride spacer mask. A dielectric is formed upon the channel length and the method continues by forming a gate layer over the plurality of channels. Because of the inventive method and the starting scale, each of the plurality of channels is narrower than the mean free path of semiconductive electron flow therein.
    Type: Grant
    Filed: December 13, 2004
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventor: Brian Doyle
  • Patent number: 7183648
    Abstract: A method comprising: coating a conductive bump on a first substrate with a conductive material to form a coated conductive bump; coating a conductive bump on a second substrate with a conductive material to form a coated conductive bump; and bonding the coated conductive bump on the first substrate to the coated conductive bump on the second substrate to electrically connect the first substrate to the second substrate.
    Type: Grant
    Filed: June 4, 2004
    Date of Patent: February 27, 2007
    Assignee: Intel Corporation
    Inventors: Shriram Ramanathan, Sarah E. Kim