Abstract: A die frame logic analyzer unit. For one aspect, a programmable logic analyzer unit is provided, wherein at least a first portion of the programmable logic analyzer unit is provided in a die frame. The programmable logic analyzer unit is to test a function of an integrated circuit on a wafer that includes the die frame.

Abstract: A cellular automaton cache memory architecture. On a micro-processor that is also capable of executing general-purpose instructions, a cache memory is provided to store instructions and data for use by the processor. The cache memory is further capable of storing data representing a first state of a cellular automaton at a first time step, where the data is organized in cells. A cellular automaton prefetch unit prefetches data associated with a cell to be updated and a neighborhood buffer stores the prefetched data. A cellular automaton update unit provides data from the neighborhood buffer to an update engine. The update engine includes a microprocessor execution unit capable of executing at least some general purpose microprocessor instructions and updates at least some of the selected cells according to an update rule and a state of any associated neighborhood cells to provide a state of the cellular automaton at a second time step.

Abstract: An integrated circuit-based compound eye includes a plurality of photodetector elements disposed on a semiconductor substrate. A compound light directing member includes a light pipe bundle wherein at least some of the light pipes are to individually direct light energy from one or more sources onto one or more of the photodetector elements. The compound light directing member is the primary mechanism to direct light energy onto the one or more of the photodetector elements. Outputs of the photodetector elements are electrically coupled in such a way that an image associated with the source may be synthesized at output circuitry. For another aspect, a compound exposure determining member includes a plurality of light scanning elements, each of the light scanning elements including an integrated photodetector.

Abstract: In accordance with an embodiment of the present invention, a triggering event is initiated to place a processor in a low power state. The processor may or may not flush a cache upon entering the low power state depending on a power status signal. The power status signal may indicate the relative priority of power reduction associated with placing the processor in the low power state without first flushing the cache versus an increase in soft error rate in the cache associated with reducing the voltage in the low power state.

Abstract: Detail routing using obstacle carving around terminals. A terminal in an integrated circuit layout object that is separated from an obstacle by less than a spacing specified by a design rule is identified. The obstacle is carved to reduce an area of the obstacle by an overlap between the obstacle and the terminal bloated by the spacing.

Abstract: An approach for power supply noise modeling for test pattern development. For one aspect, conditions that may result in power supply noise-related failures are identified and the resulting faults are ranked.

Abstract: On-die voltage and/or frequency detectors. For one aspect, an adaptive frequency clock generation circuit includes a droop detector to detect a supply voltage level and to cause the frequency of an on-die clock signal to be adjusted accordingly.

Abstract: A demand-based method and system of central processing unit power management. The utilization of a central processing unit (CPU) during a sampling time interval is determined by measuring a time quantum within the sampling time interval during which a central processing unit clock signal is active within a processor core of the CPU. The total number of cycles of the central processing unit clock signal that are applied to the processor core and the period of the central processing unit clock signal are used to determine the time quantum. The utilization may then be expressed in terms of a ratio of the time quantum to the total time interval and used to select a processor performance mode. The CPU is then operated in the selected processor performance mode.

Abstract: A portion of a chassis comprised of a material forming a portion of the exterior of the chassis and a high-density flexible material adjacent an inner surface of the portion of the chassis with air holes formed contiguously through both the portion of the chassis and the high-density flexible material.

Abstract: A leakage compensation approach enabling full VCC precharge. An array of memory cells is coupled between a pair of bit lines. A precharge circuit precharges the pair of bit lines to substantially a supply voltage level and a leakage compensation circuit supplies a first compensation current to a first one of the bit lines to substantially compensate for leakage current supplied by the first bit line during a memory access operation directed to one of the plurality of memory cells.

Abstract: In one embodiment of the invention, an embedded controller receives an interrupt command and a query number from a system management interrupt (SMI) handler. The embedded controller generates a system control interrupt (SCI) in response to the interrupt command. A driver that receives the SCI issues a query command to the embedded controller. A routine associated with the query number is invoked in response to the query command.

Abstract: An approach for cut-point frontier selection and/or counter-example generation. Both a lazy and an eager cut-point frontier are identified. A reconvergence (or non-reconvergence) ratio is then computed for each of the frontiers and the one with the smaller (larger) reconvergence (non-reconvergence) ratio is selected as the next cut-point frontier. For another aspect, to generate a counter-example, in response to identifying a difference in output signals for a given cut-point frontier, values of eigenvariables and reconverging primary inputs are used to compute the corresponding values of the non-reconverging primary inputs. These corresponding values are then computed to be compatible with the internal signal values implied by the cut-point frontier selections that were made to expose the difference in the outputs.

Abstract: A deferred merging router. Partial feasible routing solutions corresponding to each of a subset of a set of wires to be routed are identified. The partial feasible routing solutions are then merged to identify one or more feasible routing solutions for the set of wires to be routed. In one aspect of the invention, the final routing for an integrated circuit device may then be selected from the feasible routing solutions which may be ordered by one or more user-selected cost functions.

Abstract: Layout synthesis of regular structures using relative placement. Relative placement constraint information is received. The relative placement constraint information indicates a relative placement of a plurality of layout objects with respect to each other, wherein at least a first one of the plurality of layout objects may be at a different level of hierarchy in the layout than at least a second one of the plurality of layout objects. The plurality of layout objects is then automatically placed according to the relative placement constraint information.

Abstract: Briefly, in accordance with one embodiment of the invention, a circuit includes: a physical arrangement of power transistors. The circuit is adapted to couple a node to a power bus segment. The physical arrangement of power transistors is electronically configurable, based on externally derived electrical signals, to sink power to the node from the power bus segment, source power from the node to the power bus segment, and distribute power through the node.

Abstract: A clock duty cycle correction circuit. The duty cycle correction circuit is located at a receiver in a clock distribution network to correct a duty cycle of a distributed clock signal.

Abstract: A scan cell design approach includes removing a formal verification property associated with a scan cell from a set of formal verification properties to create a reduced set of formal verification properties. A formal verification assumption verification process is then performed on a schematic using assumptions generated from the reduced set of formal verification properties. An output of the assumption verification process indicates whether there is a potential contention site at logic coupled to the output of the scan cell.

Abstract: An output-relative signal receiver to test an integrated circuit that provides an output-relative data signal. The output-relative signal receiver receives the output-relative data signal and a corresponding output strobe signal from an integrated circuit device and produces a test strobe signal derived from the output strobe signal. The test strobe signal is used to test a feature of the integrated circuit device indicated by the output-relative data signal.

Abstract: A high-speed, state-preserving, race-reducing, wide-pulsed clock domino design style. For one aspect, a pipestage in accordance with the wide-pulsed clock design style includes one or more domino logic stages and a wide-pulsed clock generator to provide a wide-pulsed clock signal to control evaluation of the one or more domino logic stages in response to receiving a two-phase input clock signal. The wide-pulsed clock signal has a pulse width that tracks a phase width of the input clock signal over a first frequency range where the first frequency range extends at least from a predetermined fraction of a nominal clock frequency to an upper frequency limit for the circuit. For one aspect, ratio logic is coupled to at least one of the domino stages. The wide-pulsed clock signal provides sufficient time for the one or more domino logic stages to evaluate while preventing infinite or very long contention in one or more ratio logic stages when the input clock signal is stopped or slowed down significantly.

Abstract: An approach for precise signal interpolation. For one aspect, each of the linear resistive elements in a first array of selectable linear resistive elements receives a first input signal. Each of the linear resistive elements is coupled to provide an output signal on a first output signal line. A variable bandwidth-compensating circuit is coupled to the first output signal line to compensate the bandwidth of the output signal.