Abstract: A multiple stage delta sigma converter includes a first delta sigma modulator providing a first modulator output signal, a second delta sigma modulator providing a second output signal, and a pulse wave modulator for generating formatted output wherein the level (width) of the formatted output is dependent upon the first modulator output and the timing (delay) of the formatted output is dependent upon the second modulator output. The second modulator output is also based upon the first modulator feedback signal. The second modulator quantizer output and feedback signal are constrained by an output of the first converter. A 1 bit digital to analog converter connected to the output of the PWM converts the formatted output signal to an analog signal.

Abstract: A sampled amplitude read channel is disclosed for disk storage systems that employs an EPR4 remod/demod sequence detector. To reduce the complexity of timing recovery, gain control and adaptive equalization, the channel samples are initially equalized into a PR4 partial response so that a simple slicer circuit can generate estimated sample values. The PR4 equalized channel samples are then passed through a 1+D filter to generate EPR4 equalized channel samples which are processed by an EPR4 Viterbi sequence detector to generate a preliminary binary sequence. The preliminary binary sequence is remodulated into an estimated or ideal PR4 sample sequence which is subtracted from the PR4 equalized channel samples to generate an error sample sequence. An error pattern detector processes the error sample sequence to detect the dominant error events associated with the EPR4 Viterbi sequence detector.