Abstract: A method of forming an interconnect bump structure (32, 33). Under Bumb Metalization 11 (UBM) comprising a chrome layer (16), a copper layer (36), and a tin layer (40) is disclosed. In one embodiment, eutectic solder (45) is then formed over the UBM (11) and reflowed in order to form the interconnect bump stucture. In another embodement, a lead standoff (46) is formed over the UBM (11) before the formation of the eutectic solder (48).

Abstract: A voltage regulator with automatic accelerated aging circuit (200) includes a comparator (202), a switched voltage divider (204), and a current-to-voltage converter (224). The voltage regulator (200) is implemented in an integrated circuit and monitors a power supply voltage provided to the integrated circuit. When the power supply voltage is within a first normal voltage range, the voltage regulator (200) provides a normal internal supply voltage to the integrated circuit. When the power supply voltage is within a second higher voltage range, the voltage regulator (200) automatically provides a higher than normal internal power supply voltage to the circuits of an integrated circuit for causing accelerated aging of the integrated circuit during burn-in reliability testing.

Abstract: A non-volatile memory (12) such as FLASH provides for two modes of operation: command mode and memory mode. Read requests in command mode read non-volatile memory status information, such as from status registers (29). Reads in memory mode return data stored in a non-volatile memory array (20, 22). A command mode read is distinguished from a memory mode read by whether a command mode indication is received within the same memory cycle as a read indication. The command read indication may be an operand address within a prespecified range of memory addresses or through a dedicated input pin. The prespecified memory addresses may be memory-mapped to status registers (29), allowing reads of status registers (29) when an operand address is within the prespecified range without the necessity of entering and leaving command mode, and otherwise to data (20, 22) stored in the non-volatile memory (12).

Abstract: A data processing system (20) has a central processing unit (CPU) (22) and a memory (30) for storing an exception table. The exception table is mapped in the memory (30) in consecutive segments, with each segment for storing a predetermined number of instructions for executing the exception. By asserting a control bit, the exception table can be relocated, or remapped, and compressed into a jump table. The jump table stores only jump instruction for branching to the exception routines, which are relocated to other memory locations. The jump table is generated from the starting addresses of the exception routines. Relocating the exception routines allows for more efficient use of internal memory space of the data processing system (20).

Abstract: A pipelined dual port integrated circuit memory (20) includes an array (21) of static random access memory (SRAM) cells, wherein each of the memory cells (80) is connected to a single word line (72) and to a single bit line pair (74, 76). Each port's access is performed synchronously with respect to a corresponding clock signal. The two clock signal signals are asynchronous with respect to each other. When access requests are received from both ports substantially simultaneously, an arbitration circuit (24) determines which port receives priority. The port which receives priority accesses the array (21) first. The arbitration circuit (24) ensures that substantially simultaneous access requests are serviced sequentially and occur within a single cycle of a corresponding clock signal.

Abstract: A semiconductor device (10) includes a bump structure that reduces stress and thus reduces passivation cracking and silicon cratering that can be a failure mode in semiconductor manufacturing. The stress is reduced by forming a polyimide layer (16) over a passivation layer (14). The polyimide layer (16) is extended beyond an edge of the passivation layer (14) over the metal pad (12). A solder bump (22) is composed of a eutectic material and is formed on the metal pad (12) and on the polyimide layer (16). The polyimide layer (16) prevents the solder bump (22) from contacting the passivation layer (14). This is useful for electroless or electroplating technology and may also be useful in other types of bump forming technology such as C4 and E3.

Abstract: Testing of a multi-module data processing system (20) includes performing a functional test on a module (42, 44, 46, 48, 50, 54) concurrently with an erase operation of a non-volatile memory module (34, 36). Because the erase operation requires multiple clock cycles to complete, and little or no interaction with a tester, a set of test patterns may be run on one or more of the modules (42, 44, 46, 48, 50, 54) while the erase operation is being performed. Between each test pattern, a special reset signal is provided to a reset unit (39) of a system integration unit (38). The special reset signal resets the modules (42, 44, 46, 48, 50, 54), without affecting the erase operation of the flash memory module (34, 36), in order to perform each test of the modules (42, 44, 46, 48, 50, 54) from a known state. Concurrent testing in this manner reduces the time required to test a multi-module data processing system.

Abstract: A data processing system (10) includes a mechanism for preventing DST line fetches from occupying the last available entries in a cache miss queue (50) of the data cache and MMU (16). This is done by setting a threshold value of available cache miss queue (50) buffers over which a DST access is not allowed. This prevents the cache miss queue (50) from filling up and preventing normal load and store accesses from using the cache miss queue (50).

Abstract: A voltage generation circuit (60, 62) is adapted to sense voltages on multiple windings (82, 84, 86) of a multi-phase brushless DC motor (22) during successive intervals of a rotation of the motor (22) in which the respective windings (82, 84, 86) are not being driven. The voltage generation circuit (60, 62) provides a different output voltage from the voltage used to drive the motor (22). In one embodiment, the voltage generation circuit (60, 62) includes a voltage boosting circuit (62) to increase the output voltage above the drive voltage. This voltage generation circuit (60, 62) may be advantageously combined with an electrically programmable read only memory (EPROM) (56) on a single integrated circuit chip. The voltage generation circuit (60, 62) generates the EPROM programming voltage without the need for a costly on-chip charge pump or off-chip DC-DC converter.

Abstract: A memory device (50) contains a first array of memory (12) and a second array of memory (14). The arrays (12 and 14) are coupled to four segmented current data buses (iGDLs) (16, 18, 20, and 22). When in a x36 word mode of operation, the current data buses (16, 18, 20, and 22) are wired to communicate directly with output buffers (56-59) through several current-to-voltage converters (24-31). When in a x18 word mode of operation, the current data buses (16, 18, 20, and 22) are wired to communicate through the converts (24-31), through a voltage bus (52 and 54, see also FIG. 3), to the output buffers (56-59). The change in wiring for x36 word mode versus x18 word mode is done either by a top-level metal option in fabrication or by user software programming whereby the device (50) is easily wired into one of two configurations while maintaining an advantageous speed/power product.

Abstract: A method for multiple context analysis of software applications in a multiprocessing (22, 23), multithreaded computer environment utilizes instrumentation code inserted (54, 55) into the applications. For each execution (67) of the application (60), a context set is selected (62). Execution of the instrumented code (67) provides information for analysis in an instrumentation buffer (82) addressed by a reserved register (80) or buffer pointer. The operating system is responsible for providing in the reserved register (80) the address of the instrumentation buffer (82) appropriate for each instrumented context executed. When the application (60) is done with an instrumentation buffer (82), the buffer may be processed by filter software (68).

Abstract: An equalizer (106, 146) for use in systems such as an asymmetric digital subscriber line (ADSL) transceiver (5) reduces the number of calculations required for updating the equalizer coefficients. The equalizer (106, 146) takes advantage of the substantially symmetrical phase and amplitude distortion of the signal constellation, which causes both the amplitude and the phase relationship of the calculated error term for each constellation point to be equal. Instead of performing a full complex multiplication, the equalizer (106, 146) uses some but not all of the product terms between the real and imaginary components of the calculated error term and the conjugate of the received data estimate in the coefficient update calculation. The result is then scaled to account for the missing terms. The resulting equalizer (106, 146) requires fewer calculations for coefficient updating.

Abstract: A test system (10) for testing real-time angle/time based control systems includes a digital signal generator (16), a multi-channel pulse analyzer (22), and a test system host (12). The test system host (12) controls the execution of a user generated test script. The script specifies test stimuli, external angle/time event interrupts for use by the digital signal generator (16) to a device under test (DUT) (20), and angle/time triggers used by the analyzer (22) to test the DUT (20). Using the test stimuli and external angle/time event interrupts, the DUT (20) is exercised to determine whether or not the DUT (20) and corresponding control system software operate properly. Output data from the DUT (20) are monitored by the pulse analyzer (22), which records the output data based on information specified in the script. Test results are then retrieved by the test system host (12).

Abstract: A method is presented for performing model checking of an integrated circuit design that avoids the need for construction of an environment model by the use of constraints (44). The method supports an assume/guarantee style of reasoning to ensure that the constraints (44) are a true abstraction of the actual environment in which the integrated circuit is designed to operate. The constraints (44) may be used to provide primary inputs for a design under analysis (DUA) (16). Also, the constraints (44) may refer to internal states and to outputs of the DUA (16). In addition, monitors (42) may be used to monitor the inputs to the DUA (16). The constraints (44) can then be used with the monitors (42) to specify complex sequential environment properties.

Abstract: A floating-gate non-volatile memory (30) uses a relatively-low threshold voltage to define a programmed state. The memory (30) compensates for fast program cells by providing program pulses which increase in length and magnitude while the cells are being programmed. Between each program pulse the memory (30) determines whether selected cells have been adequately programmed. The memory (30) ceases applying the series of pulses to each cell when it has been adequately programmed. Thus the memory (30) avoids the over-program condition instead of compensating for it.

Abstract: A data processing system (10) having an access protect unit (20) for tracing memory accesses. A trace bit (50) is associated with each page of memory and when set generates an interrupt signal on a first valid access to the page. The access protect unit (20) supports trace in both supervisor and user mode without the need for an emulation system or an on-chip emulator. Tracing is done without providing "backdoor" access to the central processing unit (CPU). The access protect unit (20) allows programmable memory segment tracing. Signature monitoring of memory accesses is accomplished by storing sequential memory segments in a plurality of registers.

Abstract: A pipelined data processing system (10) includes a scheme for selectively controlling forward branch prediction and backward branch prediction, as well as prefetching and conditional execution of instructions for various branch scenarios. A three bit programmer accessible control field (19) is used to specify the type of activity to be used with a conditional branch instruction by allowing the independent control of prefetching of instructions for both forward and backward conditional branches. Also, control over conditional execution is provided for both forward and backward branches. By allowing independent control of forward and backward branch prediction and conditional execution, pipeline stalls can be reduced and more flexible program execution can be achieved for different environments.

Abstract: A method of detecting defective CMOS devices by quiescent current (IDDQ) behavior using a monitor circuit resident in the expendable areas of a die and/or wafer. One embodiment of the present invention incorporates a monitor unit (10) into the scribe grid of a wafer, where pads (2, 3, 4) are built in the corners of the die (5) and connected to the monitor unit (10) via metal connects in the wafer. The monitor unit (10) determines defective die based on IDDQ as expressed by decay of voltage (Vdd) in time, where Vdd is supplied to a die by way of a switch (20) in the monitor unit (10). Alternate embodiments incorporate various configurations and incorporate functional and other tests into a wafer level test system. Other embodiments provide the monitor unit on the die, allowing for later testing and user confirmation.

Abstract: A method for model reduction (48) for electronic circuit simulation (52) of an electronic circuit using multipoint matrix Pade approximation is provided herein. Using the method, state equations are generated from a linear circuit to be analyzed. One or more expansion frequencies and a number of moments for each of the one or more expansion frequencies are provided. Starting block Lanczos vectors using a first expansion frequency of the one or more expansion frequencies and the state equations are generated. New block Lanczos vectors are generated from the starting block Lanczos vectors. The new block Lanczos vectors are scaled and normalized. Breakdowns in the new block Lanczos vectors are detected and treated to generate new starting block Lanczos vectors.

Abstract: A loop cache (26) is used in a data processing system for supplying instructions to a CPU to avoid accessing a main memory. Whether instructions stored in the loop cache can be supplied to the CPU is determined by a distributed TAG associated with the instruction address computed by the CPU. The instruction address includes an LCACHE index portion (42), an ITAG portion (44), and a GTAG (46). LCACHE index (42) selects corresponding locations in each of an ITAG array (50), an instruction array (52), and a valid bit array (54). A stored GTAG value (48) is chosen irrespective of where LCACHE index (42) is pointing. The GTAG portion of the instruction address (40) is compared to the stored GTAG value (48). The ITAG portion (44) of instruction address (40) is compared with the indexed ITAG of the ITAG array (50). If both the GTAG and ITAG compare favorably, the instruction is supplied from the loop cache to the CPU, rather than from main memory.