Abstract: A projection system employs a convex reflecting mirror to disperse a projected image onto the inner surface of a screen enclosing a spherical or other three-dimensional space. When the screen is a spherical, translucent rear-projection screen, the projection system produces a display of substantially spherical form viewable from outside the enclosed space. When the screen is opaque and of spherical or other three-dimensional form, the projection system produces a three-dimensional image surrounding a viewer.

Abstract: Separate heating elements are embedded in a printed circuit board near integrated circuit (IC) packages or other parts mounted on the circuit board. Each heating element supplies heat to the part residing near it in response to an input voltage pulse. The heating elements are used to selectively melt solder or adhesives attaching the parts to the circuit board so that they can be easily removed or to temporarily melt solder or cure adhesive when the parts are mounted on the circuit board. The heating elements are also used to supply heat to IC packages for regulating their operating temperatures.

Abstract: A low-profile, short signal path relay assembly implementing several relays for use in an integrated circuit tester, a digitizer or other equipment requiring multiple relays, includes a chassis and a signal board mounted within the chassis. Each relay includes a control rod slideably mounted within the chassis above the signal board, a resilient contact arm mounted on the signal board below the control arm, and a coil assembly mounted adjacent to a magnetic end of the control rod. A spring is positioned between the control rod and the chassis so that it normally forces the control rod to slide in a direction away from the coil assembly. However when a current is applied to the coil assembly it produces a magnetic flux attracting the magnetic end of the control rod toward the coil assembly.

Abstract: A triggered integrated circuit (IC) tester in accordance with the invention organizes a test of an IC into a succession of test cycles. A vector generated prior to the start of each test cycle references the test activities to be carried out during the test cycle. The tester generates a set of N periodic timing signals, T0 through T(N−1), each having a period equal to the duration of one test cycle with the timing signals being distributed in phase so that their edges evenly divide each test cycle into N intervals. Each test cycle nominally starts on an edge of the T0 signal, and each vector referencing a test event also indicates a nominal time delay following the start of the test cycle at which the event is to occur by referencing one of the timing signals T0 through T(N−1). However whenever the tester receives an input trigger signal edge, it determines an offset between the most recent T0 signal edge and the occurrence of the trigger signal edge.

Abstract: An integrated circuit (IC) tester employs a pattern generator including an instruction processor executing an algorithmic program stored in a program memory. The program defines a sequence of vectors defining test activities to be carried out during successive cycles of a test on an IC. In the course of executing the program, the instruction processor stores in various registers and counters “program status” data that the processor uses to keep track of program execution. The status data may include, for example, the current program memory address, loop and repeat counts, return addresses and the like. The pattern generator also includes a random access “program status” memory for storing a selected portion of the program status data at selected points during a test.

Abstract: A high-speed N×M crosspoint switch selectively routes input signals arriving at any of N input terminals to one or more of M output terminals through a switch cell array having N rows and M columns of switch cells, each for selectively providing a signal path between one input terminal and one output terminal. Each switch cell contains a first memory cell holding a data bit, a second memory cell holding a control bit, and a transistor for making or braking a signal path in response to the control bit. This switch cell architecture enables the crosspoint switch to operate in normal, implied disconnect and broadcast modes. In the normal mode a controller creates a routing pattern by writing data bits to the second memory cells and then signals all switch cells to transfer their data bits into the first memory cells. In the implied disconnect mode, when any cell of a column is signaled to make a path, all other cells along that column automatically break their paths.

Abstract: A gain control circuit for generating a differential output signal in response to a differential input signal with a gain controlled by an input control signal employs two asymmetric field effect transistors (FETs) as a linear, voltage-controlled resistor. The FETs are interconnected drain-to-source with the control signal being applied to their gates so that their combined channel current is a substantially linear and symmetric function of the input control signal voltage. The gain control circuit includes two bipolar transistors, with the differential input signal being applied across their bases and the differential output signal being developed across their collectors. A resistor links the emitters of the two transistors, sources are applied to the emitters, and a pair of resistors links each collector to a source of bias voltage. The FET-based voltage-controlled resistor may be connected either between the collectors or between the emitters of the two transistors.

Abstract: An arbitrary waveform generator (AWG) for producing an analog output current signal includes a random access memory (RAM), a programmable logic device (PLD), a programmable pattern generator, several digital-to analog converters (DACS) and a current multiplexer. The RAM store data sequences representing the analog waveform to be generated. The pattern generator read addresses the RAM causing it to sequentially read out its stored data sequence to the PLD. The PLD routes selected fields of each data sequence word to one or more of the DACs in response to timing signals provided by the pattern generator. Each DAC produces an output current of magnitude determined by its input waveform and range data. The pattern generator also signals the analog multiplexer to sum currents produced by one or more selected DACs to produce the AWG output waveform.

Abstract: In an integrated circuit (IC) design, a set of K×N clocked IC devices (“syncs”) such as flip-flops and latches are organized into K clusters of N syncs each, with each cluster being clocked by a separate clock tree buffer. An improvement to a conventional “K-center” method for assigning syncs to clusters is disclosed. The improved method, which reduces the separation between syncs within the clusters, initially employs the conventional K-center method to preliminarily assign the K×N syncs to K clusters having N syncs per cluster. The improved method thereafter ascertains boundaries of rectangular areas of the IC occupied by the separate clusters. When areas of any group of M>1 clusters overlap, the K-center meth is repeated to reassign the set of M×N syncs included in e M overlapping clusters to a new set of M clusters. The new set of M clusters are less likely to overlap.

Abstract: A field programmable gate array (FPGA) and a decryption circuit are implemented within a common integrated circuit (IC) or within separate ICs enclosed within a common IC package. The decryption circuit decrypts an input FPGA program encrypted in accordance with a particular encryption key and then writes the decrypted FPGA program into the FPGA. Thus an FPGA program encrypted in accordance with a particular encryption key can be used to program only those FPGAs coupled with a decryption circuit capable of decoding the encrypted FPGA program in accordance with that particular encryption key. Since the decryption circuit and the FPGA are implemented in the same IC, or within the same IC package, the decrypted FPGA program the decryption circuit produces cannot be readily intercepted and copied.

Abstract: An arbitrary waveform generator (AWG) generates an output signal that linearly ramps between discrete levels to approximate a smoothly varying waveform. The AWG includes a digital-to-analog converter (DAC) formed by a set of N ramp generators, with each ramp generator producing output currents that ramp at adjustable rates between discrete levels in response to a change in state of an input waveform data bit. The output currents of all N ramp generators of the DAC, which have separately weighted magnitude levels, are summed and converted to a proportional voltage to produce the AWG's output signal.

Abstract: A main power supply continuously provides a current to a power input terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases during state changes in synchronous logic circuits implemented within the DUT. To limit variation (noise) in voltage at the power input terminal arising from these temporary increases in current demand, a charged capacitor is connected to the power input terminal during each DUT state change. The capacitor discharges into the power input terminal to supply additional current to meet the DUT's increased demand. Following each DUT state change the capacitor is disconnected from the power input terminal and charged to a level sufficient to meet a predicted increase in current demand during a next DUT state change.

Abstract: The invention provides a method for filtering motion effects from a de-interlaced image and an apparatus associated therewith. The method assumes that the de-interlaced image is formed by a combination of a first interlaced image and a second interlaced image. A first step in the method is to interpolate an interpolated line between two lines in a region of the first interlaced image. A variance value is then determined between the interpolated line and a corresponding line in a corresponding region of the second interlaced image. A threshold value will have been predetermined in the system and the variance value is compared against that threshold value. If the variance value is less than the threshold value then the correlation is strong and the corresponding line is displayed in the de-interlaced image. Otherwise if the variance value exceeds the threshold value then the interpolated line is displayed. This process is repeated for each pixel until the entire image is displayed.

Abstract: A random access memory (RAM) having N addressable storage locations is addressed by input data specifying a signal delay, and the RAM reads out control data controlling the delay of a delay circuit. A linearization system automatically adjusts the value of the control data stored at each of the RAM's N addresses so that the delay provided by the delay circuit is a linear function of the value of the input data. The linearization system provides two periodic reference signals (“beat” and “clock”) wherein the period PB of the beat signal and the period PC of the clock signal are related by the expression PB=PC(N+1)/N. The linearization system iteratively adjusts the control data stored at each RAM address so that when the RAM continuously reads out the control data stored at the Kth RAM address, the Kth edge of the beat signal and every Nth edge thereafter substantially coincides with an edge of the delay circuit output signal.

Abstract: A relay includes contacts residing within a glass tube. A coil surrounding the tube and a switch are connected in parallel between two terminals of the relay. A current source supplies a current to the coil and switch. When the switch is open, substantially all of the current passes through the coil and the coil produces a sufficient amount of magnetic flux to close the relay's contacts. When the switch closes, it shunts a sufficient amount of the current away from the coil to reduce the magnetic flux it produces below the level needed to keep the contacts closed. The current source is sized so that the coil requires relatively few turns, thereby allowing the relay to be relatively thin. The coil is formed by a conductor embedded in an insulating substrate surrounding the tube.

Abstract: An integrated circuit (IC) tester includes set of tester channels, each for carrying out a test activity at a separate terminal of an IC device under test (DUT) during each cycle of a test. Each tester channel includes a disk for storing several instruction sets, each including instructions and control data defining a separate test. To set up the tester for a test, a host computer sends a command to each channel identifying the instruction set to be used. Each channel then executes the instructions of the identified set during the test. Each channel also includes a high-speed instruction memory that can read out instructions at a higher rate than the disk. Before starting a test, each channel moves instructions covering high-speed portions of the test from the disk to the instruction memory. Thereafter, during those high-speed portions of the test in which instructions must be read out and executed at a high rate, each channel acquires those instructions from its instruction memory.

Abstract: A built-in replacement analysis (BIRA) circuit allocates spare rows and columns of cells for replacing rows and columns of an array of memory cells in response to an input sequence of cell addresses, each identifying a row address and a column address of each defective cell of the cell array. The BIRA subsystem, including a row register corresponding each spare row and a column register corresponding to each spare column, responds to incoming cell addresses by writing their included row address into the row registers, by writing their column addresses into the column registers, and by writing link bits into the column registers. Each link bit links a row and a column register by storing row and column addresses of a defective cell. The BIRA subsystem also writes a “multiple cell” bit into each row register to indicate when the row address it stores includes more than one defective cell.

Abstract: A system for testing both simulated and real versions of an integrated circuit (IC) includes an IC simulator, a simulator manager, an IC tester, and a tester manager. The IC simulator simulates response of the IC to a set of simulated IC input signals by producing a set of simulated IC output signals. The simulator manager, programmed by a user-supplied test bench file, provides the simulated IC input signals to the simulator during the simulation. During the simulation, the simulator manager also generates a set of waveform data sequences, each representing periodically sampled values of a corresponding one of the simulated IC input and output signals. The IC tester includes a separate channel corresponding to each real IC input and output signal. The tester manager converts the waveform data sequence corresponding to each simulated IC input and output signal to a separate set of instructions provided as input to a corresponding one of the IC tester channels.

Abstract: A control unit automatically adjusts the supply voltage to a differential amplifier so that the amplifier has a common mode output voltage matching an input control voltage. The control unit employs circuit elements analogous to circuit elements forming the differential amplifier to generate a reference voltage in response to the supply voltage wherein the reference voltage is an estimate of the amplifier's common mode output voltage. An operational amplifier receiving the control voltage and the reference voltage as inputs, adjusts the supply voltage so the reference voltage matches the control voltage, thereby ensuring that the amplifier's common mode output voltage matches the control voltage.

Abstract: A probe assembly for probing pins of an integrated circuit (IC) includes a base providing a set of solder-coated contacts arranged to contact a corresponding set of IC pins when the base is placed over the IC pins. The base also includes an heating element for briefly delivering heat to the contacts so that when the base is placed over the IC with the contacts in resting on the IC pins, the heat provided by heating element temporarily melts the solder coating on the contacts. Thereafter, the solder cools and solidifies to form a firm bond between the contacts to the IC pins. The heating element suitably comprises material that generates substantial heat in response to a voltage pulse applied across the heating element or alternatively may act as a heat conductor for conducting heat from an external heat source to the contacts.