Abstract: A pipelined alignment shifter allows transfer of strings of bytes between memories which are non-aligned in computer systems or serial communications and networking with the memories arranged in N fields of B bits, where N and B are integers. The shifter has B copies of N-1 storage elements connected to N copies of N to 1 (N:1) multiplexers. An enable signal E is commonly transmitted to each copy of N-1 storage elements to cause each N-1 storage element, e.g., a latch or a register, to output a previously stored input and to store a corresponding input. A selection signal S indicative of the offset difference between the memories is commonly transmitted to each copy of N:1 multiplexer for realignment of non-aligned boundaries in data transfer mechanisms such as Direct Memory Access (DMA) controllers.