Abstract: A method and apparatus virtualizes file access operations and other I/O operations in operating systems by performing string substitutions upon a file paths or other resource identifiers to convert the virtual destination of an I/O operation to a physical destination. A virtual file system translation driver is interposed between a file system driver and applications and system utilities. The virtual file system translation driver receives file access requests from the applications and system utilities, and translates the file path to virtualize the file system. In a first embodiment, the file system is partially virtualized and a user can see both the virtual file paths and the physical file paths. In second and third embodiments, the file system is completely virtualized from the point of view of the applications and system utilities. In the second embodiment, a user may start with a physical file system, and virtualize the file system by installing the virtual file system translation driver.

Abstract: A wireform bracket provides a simple, elegant, low-cost solution for managing a large number of cables, while also allowing ample airflow at the back of a computer system. A wireform bracket in accordance with the present invention includes a plurality of bends, with each bend proximate a connector on the backplane of a computer system when the wireform bracket is attached to the back of the computer system. As cables are connected to the back of the computer system, each cable is fastened to the nearest bend using a tie-wrap, or some other cable fastening method known in the art. The present invention minimizes potential strain at the connectors by shifting any strain to the point at which the cable is attached to the wireform bracket, while also minimizing the disruption of airflow in the area immediately behind a computer system. In one embodiment, a wireform cable is formed from a ⅛ inch thick piece of steel wire, though other materials and thicknesses may be Mused.

Abstract: A computer system includes a data structure that maintains availability status for registers of a processor of the computer system, wherein the availability status indicates whether an instruction attempting to read a particular register will stall. The computer system also includes instruction decode and execution circuitry that is capable of decoding and executing one or more instructions that alter a path of program execution based on the availability status of one or more of the registers. In one embodiment, a latency probe instruction retrieves the availability status of a register from the data structure and stores the availability status in a register. Thereafter, a conditional branch instruction determines the path of program execution based on the availability status stored in the register. In another embodiment, a conditional branch instruction queries the data structure directly to determine the availability status of a register, and determines the execution path based on the availability status.

Abstract: An assembly comprising a housing and a circuit board is designed to facilitate a simplified method of assembling the circuit board into the housing, along with a simplified method of coupling the signals on the circuit board to other circuits. The circuit board is guided into place by a pair of slots, with each slot located proximate an end of the housing. The housing includes a support member that has a deflection/retention feature that extends above a plane formed by the circuit board after the board has been assembled to the housing. The assembly is assembled by first partially inserting one end of the board into a slot and pressing the other end of the board toward another slot, with a curved guide deflecting the board downward and into the other slot. When both ends of the circuit board are inserted into the slots, the deflection/retention feature is in contact with the board and flexes the board upward.

Abstract: A fly-by checksum is generated at a lower layer of the protocol stack and travels up to a high layer of a protocol stack to verify incoming data. In one embodiment, a network adapter comprises includes one or more protocol stacks and a LAN controller that includes a fly-by checksum generation unit. A checksum algorithm is registered with the fly-by checksum generation unit for each protocol layer that is to receive a fly-by checksum. As an incoming packet is transferred from network media to network adapter memory, the fly-by checksum generation unit calculates a fly-by checksum for each checksum algorithm that has been registered. After the fly-by checksums are complete, they are transmitted to the network adapter memory and are transmitted up the appropriate protocol stack within a checksum channel. When data reaches a layer of the protocol stack for which the fly-by checksum was generated, the fly-by checksum is removed from the checksum channel and is used to verify the integrity of the data.

Abstract: A computer apparatus incorporating special instructions to force load and store operations to execute in program order. The present invention provides a new and novel store instruction that is suspended until all prior store instructions have been completed by an associated CPU. Also, a new load instruction is provided which blocks any subsequent load instructions from executing until this load instruction has been completed by an associated CPU. These instructions allow for high efficiency computer systems to be implemented which optimize instruction throughput by executing subsequent instructions while waiting for a prior instruction to complete.

Abstract: A window is attached to a bezel, housing, or other assembly. The bezel, housing, or other assembly has a series of pins surrounding an opening, and the window has a corresponding series of holes. The centers of the holes are slightly off-center from the centers of the pins in one dimension. When the window is pressed into place over the opening, the window deflects slightly. This deflection causes the edges of the holes to “dig into” the pins, and retains the window in place over the opening.

Abstract: A method verifies that a processor is executing instructions in a proper endian mode when the endian mode is changed dynamically. In accordance with the present invention, a test suite written and compiled in big endian mode is loaded into memory. The test suite is converted to little endian mode and stored back to memory. Next, the processor status is changed from big endian mode to little endian mode, and the test suite is executed. Finally, the results of the test suite are examined to ensure that the processor properly executed the instructions in little endian mode.

Abstract: A method and apparatus determines interleaving schemes in a computer system that supports multiple interleaving schemes. In one embodiment, a memory interleaving scheme lookup table is used to assign memory interleaving schemes based on the number of available bank bits. In another embodiment, the percentage of concurrent memory operations is increased by assigning memory interleaving schemes to bank bits based on the classification of bank bits. The present invention supports a memory organization that provides separate memory busses that support independent simultaneous memory transactions, and memory bus segments that allow memory read operations to be overlapped with memory write operations, with each memory bus segment capable of carrying single memory operation at any given time.

Abstract: A method and apparatus link translation lookaside buffer (TLB) purge operations to cache coherency transactions, thereby allowing the TLB purge operations to be performed by hardware without significant software intervention. Computer systems having cache memories associated with multiple cache modules, such as a CPU or an I/O device, typically use a cache coherency protocol to ensure that the cache memories remain consistent with each other and with main memory. Popular cache coherency protocols usually include an INVALIDATE transaction that signals cache memories to invalidate a cache line associated with the address contained in the transaction. A TLB in accordance with the present invention will observe the physical address contained in an INVALIDATE request and determine whether address lies within the page table. If it does, the physical address into the page table will be converted into a virtual page number. The TLB will then be accessed to see if the TLB contains an entry for the virtual page number.

Abstract: A network device receives packets from a first network segment, time stamps the packets as they arrive, and transmits the packets to a second network segment. By time stamping packets as they arrive, stale packets can be identified and discarded. A stale packet is a packet that has been pending in the network device longer than an active timeout interval, which may be varied based on network traffic levels to conserve network bandwidth. Packets may also be discarded to conserve packet buffer memory in the network device. For example, when an incoming packet arrives and an output buffer in which the packet must be stored is full, the output buffer is scanned to identify and discard packets that have exceeded a minimum timeout interval, thereby allowing the incoming packet to be stored in the output buffer. Many network protocols initiate the retransmission of packets after a timeout interval has expired and an acknowledge packet has not been received.

Abstract: A method and apparatus forces synchronous operation in a system that determines a phase-based relationship between two clocks by providing selectable delays of clock and data signals. A sending IC transmits data to the receiving IC over a data bus, and provides a strobe (clock) signal to validate data at the receiving IC. The phase relationship between the strobe signal and the internal clock of receiving IC is initially unknown. Within the receiving IC, the strobe signal is used to form four clock signals that clock data into four flip flops using a round robin scheme. Each of the round robin flip flops has a valid read window, and pair of multiplexors route the outputs of the round robin flip flops to a pair of flip flops that are clocked using internal clocks of the receiving IC. A select signal in the clock domain of the receiving IC is provided to the pair of multiplexors. The select signal can have one of two possible orientations. A phase detection circuit selects the proper orientation.

Abstract: A method and apparatus automatically determines a phase-based relationship between two clocks generated from the same source. In accordance with the present invention, a clock generator provides a clock signal to a sending IC and a receiving IC. The sending IC transmits data to the receiving IC over a data bus, and provides a strobe signal that is delayed by ¼ of a cycle of the internal clock of the sending IC to validate data at the receiving IC. The phase relationship between the strobe signal and the internal clock of receiving IC is initially unknown. Within the receiving IC, the strobe signal is used to form four round robin clock signals that clock data into four flip flops using a round robin scheme. Each of the round robin flip flops has a valid read window, and pair of multiplexors route the outputs of the round robin flip flops to a pair of flip flops that are clocked using internal clocks of the receiving IC.

Abstract: A method and apparatus pre-validate regions in a virtual addressing scheme by storing both the virtual region number (VRN) bits and region identifiers (RIDs) in translation lookaside buffer (TLB) entries. By storing both the VRN bits and RIDs in TLB entries, the region registers can be bypassed when performing most TLB accesses, thereby removing region registers the critical path of the TLB look-up process and enhancing system performance. A TLB in accordance with the present invention includes entries having a valid field, a region pre-validation valid (rpV) field, a virtual region number (VRN) field, a virtual page number (VPN) field, a region identifier (RID) field, a protection and access attributes field, and a physical page number (PPN) field. In addition, a set of region registers contains the RIDs that are active at any given time.

Abstract: A run-time optimization strategy uses a trace picker to identify traces of program code in a native code pool, and a translator to translate the traces into a code cache where the traces are executed natively. Static branch prediction hints are encoded in branch instruction in the translated traces. A program module implementing the present invention is initialized with an empty code cache and a pool of instruction in a native code pool. The trace picker analyzes the instructions in the native code pool and identifies traces of instructions that tend to be executed as a group. When a trace is identified, basic blocks lying along the trace path are translated into a code cache, with static branch predictions encoded into the branch instructions of the basic blocks based on branching behavior observed when the trace is identified.

Abstract: A method and apparatus virtualizes file access operations and other I/O operations in operating systems by performing string substitutions upon a file paths or other resource identifiers to convert the virtual destination of an I/O operation to a physical destination. In accordance with the present invention, a virtual file system translation driver is interposed between a file system driver and applications and system utilities. The virtual file system translation driver receives file access requests from the applications and system utilities, and translates the file path to virtualize the file system. In a first embodiment, the file system is partially virtualized and a user can see both the virtual file paths and the physical file paths. In second and third embodiments, the file system is completely virtualized from the point of view of the applications and system utilities.

Abstract: A multi-port computer register file has shared word lines for read and write ports and storage elements that power down during write operations. Assume that a register file in accordance with the present invention has R read ports and W write ports, and R is greater than W. In such a register file, each register will be accessed by W combined read/write word lines, a single direction line, and R—W read-only word lines. The direction line is asserted during a write operation, and is not asserted during a read operation, and also allows the storage elements comprising each register of the register file to be powered down or enter a high-impedance state during a write operation. During a read operation, the direction line remains deasserted and the storage elements remain powered up and active.

Abstract: A bezel attaches to a chassis via pins that register the alignment of the bezel with respect to the chassis, and snap latches that retain the bezel to the chassis. The bezel of the present invention has one or more molded pins and one or more snap latches. The pins are tapered and extend out from the chassis farther than the snap latches. To assemble the bezel to a chassis, the pins are aligned with corresponding holes in the chassis. Since the pins are longer than the snap latches, the pins are easily positioned and partially inserted into the holes before it is necessary to depress the snap latches. Furthermore, since the pins are tapered, initial insertion of the pins into the holes is simplified. After aligning the pins and partially inserting the pins into the holes, the snap latches are depressed, thereby allowing the snap latches to be easily inserted into corresponding slots of the chassis as the bezel is pressed flush against the chassis. Thereafter, the snap latches are released.

Abstract: A method and apparatus provide redundant power by connecting power supplies in a segment or ring. In a first embodiment, a redundant power supply is provided at the "top" of a redundant power segment, with one or more computer devices coupled "beneath" the redundant power supply. If the power supply of any device fails, that device "borrows" power from the device immediately upstream in the redundant power segment. If the power supply of the device immediately upstream in the redundant power segment no longer has sufficient capacity to power its own circuits, that device borrows power form the device immediately upstream from it. This process may continue until the power requirements of all devices are met by the excess capacities of all power supplies in devices upstream from the device with the failing power supply, or until the redundant power supply is reached.

Abstract: A method and apparatus varies branch prediction strategy associated with branch instructions in a trace of program code. The present invention first profiles branch instructions within a trace to record branching behavior. Next, the present invention partitions branch instructions into groups of branch instructions that can be statically predicted and groups of branch instructions that can be dynamically predicted. Branch instructions that are profiled to have "strong" branching behavior (e.g., the same branch direction is taken 80% of the time) are placed in the group of branch instruction that are statically predicted. Branch instructions that are profiled to have "weak" branching behavior (e.g., the same branch direction is taken 60% of the time) are placed in the group of branch instruction that are dynamically predicted. Finally, branch instructions are adjusted by associating an indication of prediction strategy with each profiled branch instruction.